Just noticed this:
https://bitbucket.org/casl/shakti_public/
Probably worth keeping it in mind for the next couple years.
On Fri, Nov 17, 2017 at 9:10 PM, Bill Kontos vkontogpls@gmail.com wrote:
Just noticed this:
yeh the same team that was mentioned last week. suggestions on how to contact them appreciated.
l.
On 11/18/2017 10:44 PM, Luke Kenneth Casson Leighton wrote:
On Fri, Nov 17, 2017 at 9:10 PM, Bill Kontos vkontogpls@gmail.com wrote:
Just noticed this:
yeh the same team that was mentioned last week. suggestions on how to contact them appreciated.
l.
The first version of the shakti processor aka the extremely low voltage one, is of high interest to me. I am sure it is to Luke as well given this is his project. :)
I hope that good things come from this.
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On Sun, Nov 19, 2017 at 5:44 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
yeh the same team that was mentioned last week. suggestions on how to contact them appreciated.
From that link:
IF YOU ARE INTERESTED IN A EARLY ACCESS TO THE C-CLASS (64-BIT) PLEASE MAIL US AT: Madhusudan : gs dot madhusudan at cse dot iitm dot ac dot in Neel Gala : neelgala at gmail dot com
C class
32 and 64 bit 3-8 stage in-order core aimed at 10 Mhz - 1 Ghz controller requiremenets Optional memory protection and MMU Very low power static design varinats Fault Tolerant variants for ISO26262 applications IoT variants will have compressed/reduced ISA support Optional FPU, VPU Bus - AHB variants
To me it looks like the first one is too slow for general purpose computing, we would need the absolute maximum configuration to make something useful as a desktop chip. The I class is probably better suited.
I class
64-bit, 1-8 core, 8+ stage out of order, aimed at 200 Mhz - 2 Ghz industrial control / general purpose applications Shared L2 cache, dual threading support, SIMD/VPU BUS - Shakti NoC + AXI4
This is the HN discussion:
https://news.ycombinator.com/item?id=15684225
The lead architect of this project( username gsmadhusudan) has some more comments about it:
Yes, we will update the C Class next month since our private line has a lot of foundry specific code that needs to be removed. The I class needs more work but the design is in place. It will also move to quad issue and would be a Cortex A72/75 class core. More importantly the basic slow IPs, UART, I2C, quad/Octal SPI, SDRAM controller, JTAG, DMA, PLIC will be FPGA and silicon proven and production quality. Will be very useful to other developers (non RISC-V also) as would the AXI bus.
Cortex A72 is a pretty big core that just made it into a phone thermal budget with the first generation 16nm finfet process. One example is the kirin 950( found in the huawei Mate 8). From anandtech's review here are 2 links about power consumption:
https://images.anandtech.com/doci/9878/power-big.png https://images.anandtech.com/doci/9878/CPUVolt.png
Full review here( and please don't ask me about non-free js on the article): https://www.anandtech.com/show/9878/the-huawei-mate-8-review/3
Phones usually take around 3 watts tdp, so it looks like something of this class could fit on an eoma68 card. Obviously the "optional fpu-vpu" part remains a big question, while there also needs to be someone who think they can sell a few million of these so they get manufactured on a good enough node.
On Sun, Nov 19, 2017 at 10:52 AM, Bill Kontos vkontogpls@gmail.com wrote:
On Sun, Nov 19, 2017 at 5:44 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
yeh the same team that was mentioned last week. suggestions on how to contact them appreciated.
From that link:
thx bill
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