HDMI Layout Notes for EOMA68 Cards by Richard Wilbur Thu 3 Aug 2017
Recommendations for this Layout
Source (processor) end:
Could we shrink the via pitch between constituents of a differential pair (bring the vias of a differential pair closer to each other) and combine the anti-pads into an oval shape on each layer? This reduces fringing fields and thus parasitic capacitance.
I like the ground vias close to the signal vias between differential pairs. It would be lovely to get a ground via close to the via on HTX2P and possibly move the one between HTX2N and HTX1P closer to the signal vias (if the signal vias of pairs can be moved closer with combining the anti-pads).
What is the intra-pair skew from the processor lands to the first signal vias? I wonder if we could move the vias on the short lines a little further from the processor and make up some of the skew in that segment before we leave it?
Sink (connector) end:
Same thing for differential pair vias--HTX0 and HTX2--it would be lovely to shrink the via pitch and combine anti-pads (if possible). Again, I like the ground vias close to the signal vias HTX2P, HTX2N, and HTX0P. It would be lovely to be able to either put a new ground via closer to the signal via on HTX0N or move the one on the ground shield trace closer.
I like what you were showing on the video with the signal vias at the connector lands: putting a neck on the trace between the via and the land should dampen the spirits of the solder but not the signals.
If we could reduce the signal via pitch by combining anti-pads at the connector, we might be able to move the HTX1P and HTXCN signal vias to the other side of the lands next to the other side of the differential pair, thus equalizing the skew on the segment between the ESD chip pads and the connector pads. If that worked the final touch might be to add a ground via between DC3 pin 10 (GND) and the board edge for return current paths.
Other than that, I would try and move as much of the skew compensation close to the source of the skew as possible.
I'm not sure what I'm looking at as you mentioned the ground reference planes were solid under the HDMI differential pairs, but it looks like they have voids under the signals in the pictures. Am I seeing a negative, that there are only little strips of conductor in the ground reference plane directly under the high-frequency lines? Neither of these interpretations is very satisfactory, nor do they seem to represent reality.
Please let me know what can and can't be done and I will adjust recommendations accordingly.
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On Fri, Aug 4, 2017 at 3:24 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
HDMI Layout Notes for EOMA68 Cards by Richard Wilbur Thu 3 Aug 2017
Recommendations for this Layout
Source (processor) end:
Could we shrink the via pitch between constituents of a differential pair (bring the vias of a differential pair closer to each other)
maaayyybeee? PADS does the distances automatically, so it would involve manual editing (and second-guessing of the automated rules / best-practices for diff-pair routing in PADS)
and combine the anti-pads into an oval shape on each layer? This reduces fringing fields and thus parasitic capacitance.
https://e2e.ti.com/blogs_/b/analogwire/archive/2015/06/10/differential-pairs...
ok found it... hmmmm yeah i can see how that would work.
ok see attached little image: turns out that the GND copper flood-fill clearance is enough to *automatically* create the equivalent of what you're referring to.
I like the ground vias close to the signal vias between differential pairs. It would be lovely to get a ground via close to the via on HTX2P and possibly move the one between HTX2N and HTX1P closer to the signal vias (if the signal vias of pairs can be moved closer with combining the anti-pads).
yeah i think i can do the one on HTX2P... but it involves: *deep breath*
moving HSCL and all those other signals further over
inverting the XTAL-IN and XTAL-OUT signals so that one of them goes the *other* side of its BGA pad
moving and re-routing the PWM and EINT-0 signals (which are too close anyway) with those vias, to the XTAL signals
possibly routing HSDA round the *back*... no that takes it past the diffpairs... HHPD routing *right* instead of down... that would be okay.... it would go past the USB diff-pairs though.... i think i can tolerate that..
What is the intra-pair skew from the processor lands to the first signal vias? I wonder if we could move the vias on the short lines a little further from the processor and make up some of the skew in that segment before we leave it?
yes i was considering that - maybe just staggering the vias so for example HXTX1N and P are inverted as to how they really should be.
Sink (connector) end:
Same thing for differential pair vias--HTX0 and HTX2--it would be lovely to shrink the via pitch and combine anti-pads (if possible). Again, I like the ground vias close to the signal vias HTX2P, HTX2N, and HTX0P. It would be lovely to be able to either put a new ground via closer to the signal via on HTX0N or move the one on the ground shield trace closer.
it's virtually impossible to get anything in there, because of the three Rclamp0524p components (anti-static protection).
i'm going to move one of the rclamp0524p's so that it's directly above the other, and it *might* then be possible to fit some GND vias in there.
also i realised that the path is shorter to the DC3 connector because of the via staggering, so i will have to put a small "wiggle" into the shorter path right at that point. why? because the signals should be properly matched right up to that point.
I like what you were showing on the video with the signal vias at the connector lands: putting a neck on the trace between the via and the land should dampen the spirits of the solder but not the signals.
yehyeh.
If we could reduce the signal via pitch by combining anti-pads at the connector, we might be able to move the HTX1P and HTXCN signal vias to the other side of the lands next to the other side of the differential pair, thus equalizing the skew on the segment between the ESD chip pads and the connector pads.
yehyeh i get it.
nomnomnom....
it might just be doable. i'd have to shrink the size of the two GND pads, 16 and 4, then the vias for 14 and 6 could be moved to the other side then *diagonal* (right).... shrinking the size of 10 as well would allow the existing vias to the right of 8 and 12 to *also* be moved diagonally to the right... changing them to 0302s would give some extra clearance, it's risky but what about this isn't...
If that worked the final touch might be to add a ground via between DC3 pin 10 (GND) and the board edge for return current paths.
Other than that, I would try and move as much of the skew compensation close to the source of the skew as possible.
yehyeh *sigh* i missed that. frack. gonna have to redo the whole frackin lot, one path at a time, so i can make sure each segment is matched. frack!!
I'm not sure what I'm looking at as you mentioned the ground reference planes were solid under the HDMI differential pairs,
yes.
but it looks like they have voids under the signals in the pictures.
no,
Am I seeing a negative,
you're seeing the board pre-flood. when flooding is done it f***s things up in PADS, causes it to be very unstable (especially if you switch it to "invisible" with SPO and PO / PD keystroke commands). also massively increases the file size. also gets in the way as you can't see a damn thing.
also if it was a real-time feature the entire system would grind to a halt as it takes about ten SECONDS to recalculate the flood-fill.
and yes layers 2 and 5 are solid GND planes.
that there are only little strips of conductor in the ground reference plane directly under the high-frequency lines? Neither of these interpretations is very satisfactory, nor do they seem to represent reality.
you may be referring to the little ground tracks i added. these are there because the copper-to-everything-else clearance i set to around.... i think... 7 or perhaps 10mil, so that it doesn't get absolutely everywhere.
however i *want* the GND plane (on 1) to go into nooks and crannies.... reach the parts that other beers can't reach... only way to do that is manually.
Please let me know what can and can't be done and I will adjust recommendations accordingly.
appreciated.
well, let me try the DC3 experiment of moving the VIAs to the other side. that i feel is really important.
l.
it works! signals on layer 6 (blue) can be made properly diff-paired. only concern: both vias are now right hard-up against the board edge. but... again, their pins are directly above them, and they're leading into the metal case which is entirely shielded. so i *think* it's ok.
l.
Sent from my iPhone
On Aug 4, 2017, at 02:46, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
it works! signals on layer 6 (blue) can be made properly diff-paired. only concern: both vias are now right hard-up against the board edge. but... again, their pins are directly above them, and they're leading into the metal case which is entirely shielded. so i *think* it's ok.
I agree as this is a mid-mount connector with metal body/shield, right? The metal extends down covering the board edge, doesn't it?
Sounds like a pretty cool accomplishment. It probably looks nice, too! That's one of things I've noticed, a good design tends to have an appealing appearance.
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On Fri, Aug 4, 2017 at 9:41 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Sent from my iPhone
On Aug 4, 2017, at 02:46, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
it works! signals on layer 6 (blue) can be made properly diff-paired. only concern: both vias are now right hard-up against the board edge. but... again, their pins are directly above them, and they're leading into the metal case which is entirely shielded. so i *think* it's ok.
I agree as this is a mid-mount connector with metal body/shield, right?
yehyeh... but in one sample it had some sort of thing coming down to meet the board, but in the reel of 1500 they don't.
The metal extends down covering the board edge, doesn't it?
top and bottom (horizontally) yes, but vertically, no.
Sounds like a pretty cool accomplishment.
well i wouldn't have tried it if you hadn't pushed me
It probably looks nice, too!
it does.
That's one of things I've noticed, a good design tends to have an appealing appearance.
ah gooood. someone else who noticed that beauty and elegance seems to actually.... work.
l.
okaay, so this is what i've managed for the outgoing vias (layer 1), the two lengths are equal (to each other and including across all four pairs) and the relative positions of each via are identical.
for layer 6.... faak it's tight on space down the bottom, so i simply can't get anything but "turns" in. it'll have to go dead-straight until the other end of the board, after the PMIC, where i'll then be able to correct the length differences between the CLK pair and the other pairs.
richard you said that the difference between all pairs should be no more than 100mil, right? but that clock should be a leetle bit longer.
CLK-pairs are 57.245 (i got them to within a thousandth of a mm! 57.245 and 57.24518 how jammy is that!!)
HX2N/P are 49.something - a hell of a big difference. luckily that one's on the outside edge so i can "wiggle" it a lot :)
oh... i had another go at the USB pairs, after reading all that you recommended i wasn't happy that there was skew (which i never noticed before). the USB lines worked but there would have been quite a bit of EM.
l.
2017-08-09 12:39 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
... forgot the images...
No image's here on the list
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On Wed, Aug 9, 2017 at 1:19 PM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-09 12:39 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
... forgot the images...
No image's here on the list
argh. bletch. frick. arse. https://www.youtube.com/watch?v=tpIkDZIqnnY
damnit that'll be because i enabled attachment-stripping, didn't i.... *sigh* :)
next set...
wiggles.jpg is the layer 6 length-matching area: HX2N/P is the one that's the longest, it snakes back on itself. i length-matched all 3 signal pairs to 56.413, and left the CK lines at 57.134 just to give the tiniest bit of delay (TI recommendations iirc).
no - not even enough space to do 5.1mil / 5.0 clearance... just... too much.
the other images show the via'd portions, they're all either symmetrical or perfectly length-matched to 0.001mm.
l.
2017-08-09 15:23 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
next set...
GND shielding parallel to the differentials is interrupted quite often. Those GND tracks act as shields, for emission and reception. I'd try to put as much parallel GND as possible.
And trace the parallel GND around the via's, see attachment.
Make sure the'res as much solid GND on the layer above and below the traces, again shielding.
Also I'd personally not use curved wriggles. HF signals travel in a straight direction. With curves they start diffracting and start bouncing cross each other and might start to radiate or echo back. But I see that the community is divided on that stance.
If tight for space you can use 90% corners with a chamfered outer edge. I suppose the chamfer acts like a mirror.
https://www.maximintegrated.com/en/app-notes/index.mvp/id/5100 Figure 6
the case for GND around differential pairs cant hurt, maybe even can help. But is it better to have GND in plane below that actually is doing same things? If there is no clear path for signal to go back then I guess put GND in parallel is good but if you have clean GND below than make it somehow redundant. Or am I wrong? I am discussing these because most probably there is tight space even without GND lines...
On 10 August 2017 at 10:01, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-09 15:23 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
next set...
GND shielding parallel to the differentials is interrupted quite often. Those GND tracks act as shields, for emission and reception. I'd try to put as much parallel GND as possible.
And trace the parallel GND around the via's, see attachment.
Make sure the'res as much solid GND on the layer above and below the traces, again shielding.
Also I'd personally not use curved wriggles. HF signals travel in a straight direction. With curves they start diffracting and start bouncing cross each other and might start to radiate or echo back. But I see that the community is divided on that stance.
If tight for space you can use 90% corners with a chamfered outer edge. I suppose the chamfer acts like a mirror.
On Thu, Aug 10, 2017 at 9:14 AM, Hrvoje Lasic lasich@gmail.com wrote:
the case for GND around differential pairs cant hurt, maybe even can help. But is it better to have GND in plane below that actually is doing same things? If there is no clear path for signal to go back then I guess put GND in parallel is good but if you have clean GND below than make it somehow redundant. Or am I wrong? I am discussing these because most probably there is tight space even without GND lines...
the most amazing borad i saw was a 2-layer 5-port GbE router. man you should have seen the diff-pairs on that. it was... beautiful. every ethernet diffpair - bear in mind this is GbE with 5 ports - so that's TWENTY pairs - had GND vias equally spaced an absolute specific distance from them, absolutely regularly like clockwork every couple of mm.
what that does is make *absolutely* certain that there's no cross-talk between the diff-pairs. with only a 5 mil GND trace between pairs i am really pushing it, but there really isn't any choice here.
the first design (done by a superb senior engineer at wits-tech) didn't even have the GND separation between diff-pairs, and yet amazingly it worked. i don't feel comfortable leaving them out, but i can't get vias in at both ends on all pairs.
l.
On Thu, Aug 10, 2017 at 9:01 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-09 15:23 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
next set...
GND shielding parallel to the differentials is interrupted quite often.
because there's simply not enough space to do otherwise. if i could move the entire CPU and RAM up another 0.5mm it would be doable. but then i would have to re-route 12 signals which go around the top area of the board and that's (a) risky and (b) not enough space to do it.
Those GND tracks act as shields, for emission and reception. I'd try to put as much parallel GND as possible.
And trace the parallel GND around the via's, see attachment.
ah, got it - thanks for the tip, i thought i'd done that on all diffpairs, but i missed one. good call.
yes there's only one, because the layer 1 and layer 6 will be flood-filled and that will fill the areas that "appear" to be missed.
Make sure the'res as much solid GND on the layer above and below the traces, again shielding.
these are layer 1 and layer 6, and layer 2 and 5 are solid GND.
Also I'd personally not use curved wriggles. HF signals travel in a straight direction. With curves they start diffracting and start bouncing cross each other and might start to radiate or echo back.
mmmmm.... *stress*! anyone else feel the curves are "Bad"?
But I see that the community is divided on that stance.
If tight for space you can use 90% corners with a chamfered outer edge. I suppose the chamfer acts like a mirror.
i'd *really* prefer not to do that :)
https://www.maximintegrated.com/en/app-notes/index.mvp/id/5100 Figure 6
wow that's pretty bad-ass.
2017-08-10 10:18 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Thu, Aug 10, 2017 at 9:01 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-09 15:23 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net: Make sure the'res as much solid GND on the layer above and below the traces, again shielding.
these are layer 1 and layer 6, and layer 2 and 5 are solid GND.
I was referring mostly to layer 3 and 4. The diff pair is either on 3 or 4. If it is on 3 a slab of GND should be on 4 and vice versa.
It's 1. Vsuply + components 2. Ground 3. HF 4. HF 5. Ground 6. Vsuply + componnents
Right?
If tight for space you can use 90% corners with a chamfered outer edge. I suppose the chamfer acts like a mirror.
i'd *really* prefer not to do that :)
https://www.maximintegrated.com/en/app-notes/index.mvp/id/5100 Figure 6
wow that's pretty bad-ass.
Yeah I had read a more extensive guide in a TI pdf somewhere, can find it at the moment. But TI documentation also schizo's on curves vs. corners of 35 degrees and chamfered 90 degrees.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Thu, Aug 10, 2017 at 9:38 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-10 10:18 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Thu, Aug 10, 2017 at 9:01 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-09 15:23 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net: Make sure the'res as much solid GND on the layer above and below the traces, again shielding.
these are layer 1 and layer 6, and layer 2 and 5 are solid GND.
I was referring mostly to layer 3 and 4. The diff pair is either on 3 or 4.
no.
If it is on 3 a slab of GND should be on 4 and vice versa.
It's
- Vsuply + components
- Ground
- HF
- HF
- Ground
- Vsuply + componnents
Right?
no.
1. SIG1 + components 2. Ground 3. SIG3 4. POWR 5. Ground 6. SIG6 + componnents
there's only 3 signal layers: 1, 3 and 6. there are NO HDMI diffpairs on layer 3. i'm not happy about the fact that i have to use vias *at all* but there's no choice: layer 1 the 24mhz XTAL and the PMIC are in the way, and when you get to the DC3 connector the signals *have* to go round the back (layer 6) anyway.
l.
On 10 August 2017 at 10:45, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
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On Thu, Aug 10, 2017 at 9:38 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-10 10:18 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Thu, Aug 10, 2017 at 9:01 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-09 15:23 GMT+02:00 Luke Kenneth Casson Leighton <lkcl@lkcl.net
:
Make sure the'res as much solid GND on the layer above and below the traces, again shielding.
these are layer 1 and layer 6, and layer 2 and 5 are solid GND.
I was referring mostly to layer 3 and 4. The diff pair is either on 3 or 4.
no.
If it is on 3 a slab of GND should be on 4 and vice versa.
It's
- Vsuply + components
- Ground
- HF
- HF
- Ground
- Vsuply + componnents
Right?
no.
- SIG1 + components
- Ground
- SIG3
- POWR
- Ground
- SIG6 + componnents
this is what we have been using for our design more or less and that came with freescale reference design as well.
there's only 3 signal layers: 1, 3 and 6. there are NO HDMI diffpairs on layer 3. i'm not happy about the fact that i have to use vias *at all* but there's no choice: layer 1 the 24mhz XTAL and the PMIC are in the way, and when you get to the DC3 connector the signals *have* to go round the back (layer 6) anyway.
l.
2017-08-10 10:45 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Thu, Aug 10, 2017 at 9:38 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-10 10:18 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Thu, Aug 10, 2017 at 9:01 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-09 15:23 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net: Make sure the'res as much solid GND on the layer above and below the traces, again shielding.
- SIG1 + components
- Ground
- SIG3
- POWR
- Ground
- SIG6 + componnents
That work's as well. But the enclosure should shield very well. And there should not be a HF signals on layer 3.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Thu, Aug 10, 2017 at 10:21 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-10 10:45 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Thu, Aug 10, 2017 at 9:38 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-10 10:18 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Thu, Aug 10, 2017 at 9:01 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-09 15:23 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net: Make sure the'res as much solid GND on the layer above and below the traces, again shielding.
- SIG1 + components
- Ground
- SIG3
- POWR
- Ground
- SIG6 + componnents
That work's as well. But the enclosure should shield very well.
metal case... yes.
And there should not be a HF signals on layer 3.
USB in places but not HDMI.
l.
2017-08-10 10:18 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Thu, Aug 10, 2017 at 9:01 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-09 15:23 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
next set...
GND shielding parallel to the differentials is interrupted quite often.
because there's simply not enough space to do otherwise. if i could move the entire CPU and RAM up another 0.5mm it would be doable. but then i would have to re-route 12 signals which go around the top area of the board and that's (a) risky and (b) not enough space to do it.
I found quite some room. See attachments. Red: Easy improvement. Yellow questionable but could use some improvement. Excuse the crappy image editor it's all I have at the moment.
Also wouldn't a GND infill on the signal layers be preferable? As log not unconnected islands emerge.
On Thu, Aug 10, 2017 at 11:14 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
I found quite some room. See attachments. Red: Easy improvement.
yep, all those will be covered by flood-fill: no need to do them manually. wiggles3_mv, the HXT0 and HXT1 GND segment on the left middle, that one i got.
but near IPSOUT, top left, in wiggles_mv? no. it means moving those IPSOUT vias, and i'm not doing that. am i. can i yes. am i going to... mmmmm..... *strains*.... okayokay you twisted my arm :)
Yellow questionable but could use some improvement. Excuse the crappy image editor it's all I have at the moment.
i _like_ crappy editors, i use them all the time :) as long as it gets the job done and it doesn't take long, communicates the intent, *why* would you spend $600 and hours of time?? :)
Also wouldn't a GND infill on the signal layers be preferable? As log not unconnected islands emerge.
GND infill *is* going to be done on the signal layers. but the copper-to-track clearance is 10mil (where tracks are 5mil). so what happens is: any space smaller than 10mil does *not* get flood-filled. so i put little "leaders" - like you can see - into the areas where the beer cannot reach.
https://www.youtube.com/watch?v=ab6dJYDgj48
l.
2017-08-10 13:09 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Thu, Aug 10, 2017 at 11:14 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
Also wouldn't a GND infill on the signal layers be preferable? As log not unconnected islands emerge.
GND infill *is* going to be done on the signal layers. but the copper-to-track clearance is 10mil (where tracks are 5mil). so what happens is: any space smaller than 10mil does *not* get flood-filled. so i put little "leaders" - like you can see - into the areas where the beer cannot reach.
Ah that explains a lot indeed. Too bad the infill isn't visualized.
Sadly the space between the HDMI connectors is to small to fill. That would encapsulate the HDMI signal pairs.
LOL
On Thu, Aug 10, 2017 at 12:33 PM, mike.valk@gmail.com mike.valk@gmail.com wrote:
Ah that explains a lot indeed. Too bad the infill isn't visualized.
i can do a flood-fill and screenshot the gerber files, i'll do that for a final check.
Sadly the space between the HDMI connectors is to small to fill. That would encapsulate the HDMI signal pairs.
that's why, if you look carefully, each pair has a GND pad directly opposite it. this is by design in the MicroHDMI connector specification, it's *designed* to be 10 / 9 staggered pins.
l.
On Thu, Aug 10, 2017 at 2:01 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
GND shielding parallel to the differentials is interrupted quite often. Those GND tracks act as shields, for emission and reception. I'd try to put as much parallel GND as possible.
And trace the parallel GND around the via's, see attachment.
Make sure the'res as much solid GND on the layer above and below the traces, again shielding.
Also I'd personally not use curved wriggles. HF signals travel in a straight direction. With curves they start diffracting and start bouncing cross each other and might start to radiate or echo back. But I see that the community is divided on that stance.
I also prefer 45 degree corners to the curves. Looks like they only occur in one section.
If tight for space you can use 90% corners with a chamfered outer edge. I suppose the chamfer acts like a mirror.
https://www.maximintegrated.com/en/app-notes/index.mvp/id/5100 Figure 6
This is good advice for single-ended signals on a stripline--high-speed digital and RF. That is the situation Maxim are addressing in the referenced document. The signals we are dealing with are high-speed digital but transmitted in differential mode on a microstrip.
Single-ended signals are transmitted relative to a ground reference and so putting ground reference next to them tends to block the side-view of the antenna created by either microstrip or stripline, thus reducing radiated and coupled interference. That's a very good thing!
microstrip (The following diagrams are in cross-section perpendicular to the direction of signal transmission. Think of the signal going into the diagram away from the viewer.)
single-ended signal without ground shield traces
signal + dielectric from the side we see a dipole antenna ground -
single-ended signal with ground shield traces - + - ground signal ground - dielectric dielectrc dielectric ground ground ground ground -
(ground shield traces would need some vias to connect them with ground plane) This blocks the view of the dipole antenna from the side and reduces the size of the dipole antenna so that far field it is vanishingly small being primarily the area between the ground shield traces and the signal trace. (Far field: distance from microstrip at least 10 * separation between signal and ground shield traces.)
Since we have a different geometry, the problem changes. We are using differential microstrips. Differential-mode signals are transmitted relative to each other instead of ground. Only common-mode noise in the signals is transmitted relative to ground.
microstrip
differential-mode signal without ground shield traces
signal+ signal- dielectric dielectric ground ground ground
Here the dipole antenna is limited to area between the two signal traces, blocked on the bottom side by ground plane, and insignificant in far field (because the traces are close together, have opposite potential and currents, and the fields cancel each other).
I'm out of time to add detail or references, so sending now.
On Fri, Aug 11, 2017 at 6:15 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Also I'd personally not use curved wriggles. HF signals travel in a straight direction. With curves they start diffracting and start bouncing cross each other and might start to radiate or echo back. But I see that the community is divided on that stance.
I also prefer 45 degree corners to the curves. Looks like they only occur in one section.
yes - i was trying to save space. ok i managed to get some 45-corner wiggles in, instead. and also got the GND separation in between the CK lines up to the via.
i'd *really* like to get this done and into test, particularly the DC3 connector test PCB (first).
ok. so wiggles1.jpg is the beginning part. track-pairs remain slightly offset, if you take the difference betweeen each pair it's nearly... 8 mm because the clock lines have to go down (3mm) then right-angle (2mm) then right (2mm) just to catch up with TX2.
so they _stay_ up to 8mm out until they get to the right end.. then they wiggle again to get match-lengthed.
BUT... it just occurred to me that on the *other* side of those ESD rclamp0524p protectors the diff-pairs are all *different lengths*.
so on the other side of the rclamp0524p components all four diff-pairs will be different lengths.
would that be sufficient, do you think, richard, to satisfy the "spread spectrum" style you were thinking of?
short lengths to the RIGHT of the rclamp0524p:
TXC: 3.11mm TX0: 1.23mm TX1: 3.23mm TX2: 1.14mm
total lengths:
TXC:57.252mm TX0:56.418mm TX1:56.398mm TX2: 56.401mm
so the signal pairs are all eever so slightly different, and they're all around 0.85mm shorter than CK.
l.
btw yes i managed to move IPSOUT slightly to the right and got a GND line in between them, without too much disruption. thank you for prompting me to do that.
l.
2017-08-13 14:20 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
btw yes i managed to move IPSOUT slightly to the right and got a GND line in between them, without too much disruption. thank you for prompting me to do that.
Amazing! Just a nitpick left. You mentioned the GND flood-fill distance is 10mil. That means that GND will 10 mil removed from tracks. Personally I'd trace the GND as close as possible to the diff signals. But that may be just overcautious.
I don't have any fancy math like Richard so it might be FUD. Or just my mild form of OCD. :-)
Or is that 10mil the minimum gap size? That would make sense.
Anyway a picture of the flood-fill will reveal everything.
On Mon, Aug 14, 2017 at 7:43 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-13 14:20 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
btw yes i managed to move IPSOUT slightly to the right and got a GND line in between them, without too much disruption. thank you for prompting me to do that.
Amazing! Just a nitpick left. You mentioned the GND flood-fill distance is 10mil. That means that GND will 10 mil removed from tracks. Personally I'd trace the GND as close as possible to the diff signals. But that may be just overcautious.
ok sorry, i was slightly wrong. clearance is also 5mil but there's something called "rounding" on the flood fill which stops it from curving into tight spaces.
I don't have any fancy math like Richard so it might be FUD. Or just my mild form of OCD. :-)
:)
Or is that 10mil the minimum gap size? That would make sense.
Anyway a picture of the flood-fill will reveal everything.
attached. greyscaled (smaller). original GND tracks are still visible but they're *combined* with the floodfill.
l.
2017-08-14 9:14 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Mon, Aug 14, 2017 at 7:43 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
Anyway a picture of the flood-fill will reveal everything.
attached. greyscaled (smaller). original GND tracks are still visible but they're *combined* with the floodfill.
Looks pretty. Seeing that does raise a question too me. Is it necessary to match length between the different pairs? I didn't think that was a requirement. Because I see pairs wriggling and wasting a lot of space.
I thought that only matching was required on a single pair. Impedance matching.
On Wed, Aug 16, 2017 at 10:31 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
Looks pretty. Seeing that does raise a question too me. Is it necessary to match length between the different pairs? I didn't think that was a requirement. Because I see pairs wriggling and wasting a lot of space.
I thought that only matching was required on a single pair. Impedance matching.
that's what we've been discussing. read richard's message and my response.
l.
2017-08-16 11:33 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Wed, Aug 16, 2017 at 10:31 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
Looks pretty. Seeing that does raise a question too me. Is it necessary to match length between the different pairs? I didn't think that was a requirement. Because I see pairs wriggling and wasting a lot of space.
I thought that only matching was required on a single pair. Impedance matching.
that's what we've been discussing. read richard's message and my response.
I've read it again. But did not digest that from Richard's responses.
Inter-pair skew: Length (un)matching between two traces making op one differential pair?
Intra-pair skew: Length (un)matching between differential pairs? Not mentioned.
What else I read so far:
Possibly remove the GND traces between pairs. Differential pairs are designed to cancel each other out thus limit radiation. The pair coupling creates force to repel incoming radiation noise. Correct me if I'm wrong
The same construction as in twisted pair cables. But there you have differential pair twisting creates an even bigger effect. But there we also have types with shielding. Shielding around the whole set and even with shielding per pair. The HMDI cables I've butchered had per pair shielding and the other lines, clock, cec, etc, unshielded bundled in one extra shield.
Removing the, intra pair, GND traces improves impedance, but decreases shielding from external incoming radiation. But I suspect that effect is limited due to the GND layer below, far bigger and nearer than those traces.
Differential pairs should have a bigger, dielectric, space surrounding them than they have to each other. Because the nearer you get to a pair the less the differential cancelling effect. With the exception for GND, which should act as a sink for EM emissions.
Removing the, intra pair, GND traces won't give you more space because the pairs should keep the extra distance from each other.
Via's should occur only when, inter pair, length is matched. Differential via's should have a rounded, oval, common, dielectric, space surrounding them so the Z-axis radiation can cancel out uninterrupted.
Digital differential signals might be skewed to begin with. Limiting the differential EM canceling effect to begin with.
I'd say keep the intra pair GND traces. Maybe loose the intra pair length mathing.
There should be no electric/magnetic coupling between intra pairs. But if their length differs the parallel digital signals might become time skewed. But I doubt that on this length that would be a problem.
Richards math should help with that along with max allowed digital signal skew. Don't have the time to convert the math in a spreadsheet calculator to confirm.
2017-08-16 15:17 GMT+02:00 mike.valk@gmail.com mike.valk@gmail.com:
2017-08-16 11:33 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Wed, Aug 16, 2017 at 10:31 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
Looks pretty. Seeing that does raise a question too me. Is it necessary to match length between the different pairs? I didn't think that was a requirement. Because I see pairs wriggling and wasting a lot of space.
I thought that only matching was required on a single pair. Impedance matching.
that's what we've been discussing. read richard's message and my response.
I've read it again. But did not digest that from Richard's responses.
Inter-pair skew: Length (un)matching between two traces making op one differential pair?
Intra-pair skew: Length (un)matching between differential pairs? Not mentioned.
Ah it seems it's the other way around. Silly me. I knew why I kept away from the intra and inter prefixes. I always switch them.
The HMDI cables I've butchered had per pair shielding and the other lines, clock, cec, etc, unshielded bundled in one extra shield.
Sorry. Clock is also one of the diff-pairs. As well as pin 17 and 19, HEAC, Utilized for ARC (S/PDIF) and Ethernet. But not in the A20 so less of a problem.
Richards math should help with that along with max allowed digital signal skew. Don't have the time to convert the math in a spreadsheet calculator to confirm.
Hmm not the only ones out there with these questions.
https://e2e.ti.com/support/interface/high_speed_interface/f/138/t/267205 "intra-pair length mismatch is recommended to be less than 5mils, inter-pair length mismatch is less of a concern but the recommendation is to keep the traces <2" and keep the clock slightly longer than the data traces."
Keeping the clock longer makes sense. All the data is buffered before the clock signal arrives.
https://forum.allaboutcircuits.com/threads/hdmi-inter-intra-pair-skew-inter-... 5bits of buffer.
http://ieeexplore.ieee.org/document/1706346/ https://www.researchgate.net/publication/224650488_Effects_of_skew_on_EMI_fo... paywall, blegh. Put in a request on the second one. Let's see
https://www.infocomm.org/cps/rde/xbcr/infocomm/Dietro_HDMI.pdf That explained the "eye diagrams". Overlapping differential signals. Hmm 1bit buffer? 1920x1080p60 = 148.5 Mhz
On Aug 14, 2017, at 00:14, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Mon, Aug 14, 2017 at 7:43 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-13 14:20 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
I don't have any fancy math like Richard so it might be FUD. Or just my mild form of OCD. :-)
:)
I'm sorry if any of this looks like fancy mathematics. (As someone whose first degree is in mathematics, I thought this was all very mundane algebra at best. I didn't get into field theory, Maxwell's equations [partial differential], et cetera.)
Anyway a picture of the flood-fill will reveal everything.
attached. greyscaled (smaller). original GND tracks are still visible but they're *combined* with the floodfill.
So I enjoyed looking at the picture but I'm curious what I'm looking at. Is this one layer? Which layer? What does the black mean? What about the gray?
2017-08-17 20:59 GMT+02:00 Richard Wilbur richard.wilbur@gmail.com:
On Aug 14, 2017, at 00:14, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Mon, Aug 14, 2017 at 7:43 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-13 14:20 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
I don't have any fancy math like Richard so it might be FUD. Or just my mild form of OCD. :-)
:)
I'm sorry if any of this looks like fancy mathematics. (As someone whose first degree is in mathematics, I thought this was all very mundane algebra at best. I didn't get into field theory, Maxwell's equations [partial differential], et cetera.)
It is fancy math. And it is mundane. I didn't have the time refresh my electrical formulas and/or follow yours. So it simply needs time and attention.
Formulas don't teach you what's going on. It's applying/verifying/quantifying your understaning of the subject. Any one can apply simple formulas. But when you don't understand where they come from you are just repeating tricks with the risk of doing it wrong.
Your formulas are however infinitely more valuable then the fixed recommendations but require more time to understand, verify and use: http://www.ti.com/lit/an/spraar7g/spraar7g.pdf figure 13
That document has some nice recommendations.
I've been away from electrical calculations for 16 years now. So they need time to enter my mind again and become applicable.
Anyway a picture of the flood-fill will reveal everything.
attached. greyscaled (smaller). original GND tracks are still visible but they're *combined* with the floodfill.
So I enjoyed looking at the picture but I'm curious what I'm looking at. Is this one layer? Which layer? What does the black mean? What about the gray?
The normal traces are all in black. The GND fill is gray. If a trace is GND the fill distance is 0 if not 5 thus connecting the GND traces to the GND fill
arm-netbook mailing list arm-netbook@lists.phcomp.co.uk http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook Send large attachments to arm-netbook@files.phcomp.co.uk
I have some time today to continue this discussion.
Sent from my iPhone
On Aug 11, 2017, at 10:15, Richard Wilbur richard.wilbur@gmail.com wrote: On Thu, Aug 10, 2017 at 2:01 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
GND shielding parallel to the differentials is interrupted quite often. Those GND tracks act as shields, for emission and reception. I'd try to put as much parallel GND as possible.
And trace the parallel GND around the via's, see attachment.
Make sure the'res as much solid GND on the layer above and below the traces, again shielding.
microstrip
differential-mode signal with ground shield traces
ground signal+ signal- ground dielectric dielectric dielectric dielectric ground ground ground ground ground ground
Here the dipole antenna remains small and the half-strength fields between each signal trace and its associated ground guard shield trace work to truncate electric fields in the plane of the PCB. The fields are still insignificant in far field (because the traces are close together, have opposite potential and currents, and the fields cancel each other). It seems the best argument for including ground shield traces on this layout might be to guard against coupling signals between differential pairs that were packed in too closely to otherwise meet the recommended distance between different signal pairs. But with the dimensions of our layout being the minimum allowed by the board fabricator, the min(s) = min(w) => d = s + w + s = 3 * s.[1] So if we were to remove the ground shield traces from between differential pairs we could meet the inter-pair spacing recommendations without moving anything else. This may explain the design by the wits-tech senior engineer you mentioned which worked without ground shield traces between the differential pairs.
The ground shield traces surrounding a differential pair on the same layer will mostly block common-mode signal radiation and coupling. They will have little beneficial effect on differential signals--but can contribute asymmetric loading (lower single-ended impedance of one trace) to the differential pair (through asymmetric geometry) which will convert some differential energy into common-mode energy.
In other words, if we are expecting significant common-mode signal, whether from pathologies in the layout or incompetence of the differential-mode signal driver, then ground shield traces may be in order. Regardless, caveat emptor (let the buyer beware): 1. asymmetries in ground guard shield implementation contribute to conversion of differential signal to common-mode signal (which for a differential receiver is noise, thus lowering signal-to-noise ratio), 2. symmetric ground guard shield traces reduce the single-ended impedance of both traces of the differential pair, lowering the differential impedance of the pair. The effect is distance-dependent, the greater the spacing the less-pronounced the effect.
Another interesting reference on high-speed HDMI PCB layout is TI's SLLA324[2]. Notice how in none of the layouts pictured in Figures 4, 6, or 8 are there any ground shield traces. Judging from the eye diagrams in Figure 10, even with fairly close pair-to-pair spacing there doesn't seem to be significant cross-talk between the pairs (look for noise at transitions): 1. in the absence of ground shield traces 2. running at top speed of HDMI v1.4 (340MHz pixel clock, 1080p video, 3.4GHz data rate) 3. space between differential pairs doesn't seem to be all that large.
Figure 4 looks like it depicts a similar connector (micro HDMI <=> type D) and it looks like they have a similar pair length relationship (which, interestingly enough, they don't seem to take any pains to equalize): length(D2) < length(D0) < length(D1) < length(CLK)
So, for the HDMI differential signals' sake, we don't necessarily need: 1. Ground guard traces between neighboring differential pairs 2. Ground guard traces between HDMI differential pairs and other circuits 3. Multiple ground vias riveting along the side of the board to block emissions 4. Perfectly matched inter-pair lengths
On the other hand: 1. Ground guard traces can be important in reducing noise radiated from single-ended circuits and coupled into other single-ended circuits on the board. 2. Ground fences, traces riveted with multiple ground vias, can help even more with the goals of "reducing noise radiated from and coupled into other single-ended circuits on the board" as above.
In other words, if we had more board space there are several things we could do differently: increase differential pair trace width and spacing, ground shield trace spacing.
But as it stands I believe it will likely work fine. Without changing anything else we could drop the ground shield traces which would serve to increase our differential impedance. We would want to retain the ground vias near signal vias.
Reference: [1] HDMI, p. 5.2 [2] SLLA324, pp. 4-7
Bibliography: Texas Instruments (TI): "HDMI Design Guide", High-Speed Interface Products, June 2007, http://e2e.ti.com/cfs-file/__key/telligent-evolution-components-attachments/...
Texas Instruments (TI): SLLA324 February 2012 Application Report, "TPD12S016 PCB Layout Guidelines for HDMI ESD" http://www.ti.com/lit/an/slla324/slla324.pdf
On Mon, Aug 14, 2017 at 10:37 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
I have some time today to continue this discussion.
awesome.
So if we were to remove the ground shield traces from between differential pairs we could meet the inter-pair spacing recommendations without moving anything else. This may explain the design by the wits-tech senior engineer you mentioned which worked without ground shield traces between the differential pairs.
yehyeh. i could then move them slightly away from the edge of the board.
Another interesting reference on high-speed HDMI PCB layout is TI's SLLA324[2].
nnniiiiiice. i love it. that's exactly the same connector being used. hmmm iinteresting, they bring the vias up from underneath on all 4 diff-pairs...
So, for the HDMI differential signals' sake, we don't necessarily need:
- Ground guard traces between neighboring differential pairs
- Ground guard traces between HDMI differential pairs and other circuits
- Multiple ground vias riveting along the side of the board to block emissions
- Perfectly matched inter-pair lengths
hmmm....
On the other hand:
- Ground guard traces can be important in reducing noise radiated from single-ended circuits and coupled into other single-ended circuits on the board.
- Ground fences, traces riveted with multiple ground vias, can help even more with the goals of "reducing noise radiated from and coupled into other single-ended circuits on the board" as above.
In other words, if we had more board space there are several things we could do differently: increase differential pair trace width and spacing, ground shield trace spacing.
But as it stands I believe it will likely work fine. Without changing anything else we could drop the ground shield traces which would serve to increase our differential impedance.
i think i will do that.
We would want to retain the ground vias near signal vias.
yehyeh.
On Aug 14, 2017, at 23:39, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Mon, Aug 14, 2017 at 10:37 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
So if we were to remove the ground shield traces from between differential pairs we could meet the inter-pair spacing recommendations without moving anything else. This may explain the design by the wits-tech senior engineer you mentioned which worked without ground shield traces between the differential pairs.
yehyeh. i could then move them slightly away from the edge of the board.
I'm curious, what would you move? The goal of this was to get >= 15mil between any differential signal trace and any trace not from the same differential pair. The ground shield traces with 5mil spacing, 5mil trace width, and another 5mil spacing enforce this spacing on the differential signal traces. So if we remove the ground shield traces, and don't move anything closer, we get that spacing for previous effort.
Are you talking about moving the differential pairs further from the edge of the board? I'm guessing since there is a ground shield trace along the edge presently, that the ground shield trace would make the distance from the nearest differential trace to board edge at least s + w = 10mil. If the ground shield trace is 5mil from board edge then we have 15mil from nearest differential trace to board edge.
Another interesting reference on high-speed HDMI PCB layout is TI's SLLA324[2].
nnniiiiiice. i love it. that's exactly the same connector being used. hmmm iinteresting, they bring the vias up from underneath on all 4 diff-pairs...
I think that is to keep the path as similar for all 4 pairs as possible. Vias add delay and (if not properly tuned) reduce the impedance. So it seems they are working with the stratagem that it is better to treat each component of the signal the same.
On Wed, Aug 16, 2017 at 6:11 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
yehyeh. i could then move them slightly away from the edge of the board.
I'm curious, what would you move? The goal of this was to get >= 15mil between any differential signal trace and any trace not from the same differential pair.
ahhhh ok. i'm glad you're paying attention :)
The ground shield traces with 5mil spacing, 5mil trace width, and another 5mil spacing enforce this spacing on the differential signal traces. So if we remove the ground shield traces, and don't move anything closer, we get that spacing for previous effort.
ha!
ok.
so.
if i just take *out* the ground intermediary traces that would do the trick of bringing the impedance back up, is that right?
what would you suggest, here - leave the intermediary GND traces in or take them out.
also, i think i "Get It" about the intermediary wiggles. when the transmit end does automatic compensation that results in the signals coming out in such a way that, really, the inter-pair length-matching should be done from the *OPPOSITE* end i.e. from the CONNECTOR.
why?
because the automatic compensation will result in the signals coming out with a small delay, which by the time they go round that big set of bends they *WILL BE IN SYNC*.
ok they'll be in sync as long as all pairs are exactly the same length from that point up until they meet the connector.
so the only bit that would be out-of-sync would be that huge set of bends just after the transition from CPU-layer-1 onto layer 6, where i've had to put in huge amounts of bend-compensation.
by adding in the down-stream inter-pair compensation just before the rclamp0524p's) that *entire straight section* is out of sync... and the set of bends is also out-of-sync so it's no improvement.
Are you talking about moving the differential pairs further from the edge of the board?
yes. but from what you're saying it's not possible anyway.
Another interesting reference on high-speed HDMI PCB layout is TI's SLLA324[2].
nnniiiiiice. i love it. that's exactly the same connector being used. hmmm iinteresting, they bring the vias up from underneath on all 4 diff-pairs...
I think that is to keep the path as similar for all 4 pairs as possible.
yehyeh.
Vias add delay and (if not properly tuned) reduce the impedance. So it seems they are working with the stratagem that it is better to treat each component of the signal the same.
indeed. however i don't want to change the BOM, apart from anything that's a TI part not a "Well Known Easily Sourceable Part In The Shenzhen Huaqiang Road Eco-System".
dual rclamp0524's, one each side, it is.
l.
On Aug 15, 2017, at 23:31, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Wed, Aug 16, 2017 at 6:11 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
yehyeh. i could then move them slightly away from the edge of the board.
I'm curious, what would you move? The goal of this was to get >= 15mil between any differential signal trace and any trace not from the same differential pair.
ahhhh ok. i'm glad you're paying attention :)
I'm trying ;>)
[…]
if i just take *out* the ground intermediary traces that would do the trick of bringing the impedance back up, is that right?
Should be a major step in the right direction.
what would you suggest, here - leave the intermediary GND traces in or take them out.
My suggestion here would be to remove the GND traces between differential pairs since we have established that we can't get 15mil clearance from the differential pair traces with the GND traces in place. We don't have enough room for that.
I would also look carefully at the GND traces separating the differential pairs from board edge and other circuitry. If we can't put 15mil between the differential pair traces and these GND traces, I would remove these GND traces as well. If we have to remove the GND traces between differential pairs and other circuitry, this will at least have the happy effect of providing 15mil spacing between the differential pair and that other circuitry.
This is all based on the fact that we are using differential-mode transmission for the high-frequency HDMI signals.
also, i think i "Get It" about the intermediary wiggles. when the transmit end does automatic compensation that results in the signals coming out in such a way that, really, the inter-pair length-matching should be done from the *OPPOSITE* end i.e. from the CONNECTOR.
Maybe I misunderstood the standard because that wasn't my understanding. (All I know is second-hand because there are no freely available copies.) What I understood was: 1. The receiver has the capability to recover up to 5 bit times of inter-pair skew, resynchronizing the bit streams without any loss. 2. The standard takes this amount of time max{T(recoverable inter-pair skew)} = 5 bit times = 0.5 * T(pixel) for highest pixel clock supported under HDMI v1.4 max{f(pixel)} = 340MHz => T(pixel) = 2940ps max{T(recoverable inter-pair skew)} = 1470ps and allocates fractions of it to maximum inter-pair skew tolerances for the implementation of the HDMI transmitter (source of HDMI signal such as DVD player, video game console, or computer such as the EOMA68-A20), the HDMI cable, and the implementation of the HDMI receiver (sink of HDMI signal such as monitor, an HDMI-switching A/V receiver, an HDMI to VGA convertor).
Thus, in order to make an HDMI v1.4 standard-compliant transmitter (which is my understanding of what we are trying to do with the EOMA68-A20) we must emit from our HDMI connector an HDMI signal which exhibits max{T(inter-pair skew)} <= 0.2 * T(pixel) = 588ps This inter-pair skew can come from connector, the chip, and the PCB traces connecting them. It seems likely that the connector and the chip will likely be very minimal sources of inter-pair skew, and thus most, if not all, of the transmitter allocation falls to the PCB designer to use (or squander--depending on how you view it) in connecting the chip to the HDMI cable connector.
At the speed of propagation of signals in our microstrip differential pairs this amounts to max{length(inter-pair skew)} = v(propagation) * max{T(inter-pair skew)} = 150um/ps * 588ps = 88.2mm Toradex suggests we limit the inter-pair skew in the traces to 1/4 of that value or 0.5 * T(bit) which corresponds to a length of 22mm.
From what I've seen, even without inter-pair skew compensation in the layout the inter-pair skew you observed was ~8mm < 22mm.
because the automatic compensation will result in the signals coming out with a small delay, which by the time they go round that big set of bends they *WILL BE IN SYNC*.
ok they'll be in sync as long as all pairs are exactly the same length from that point up until they meet the connector.
so the only bit that would be out-of-sync would be that huge set of bends just after the transition from CPU-layer-1 onto layer 6, where i've had to put in huge amounts of bend-compensation.
by adding in the down-stream inter-pair compensation just before the rclamp0524p's) that *entire straight section* is out of sync... and the set of bends is also out-of-sync so it's no improvement.
If this is indeed how it works then I'll need to rethink my recommendations. (I outlined my understanding above.)
Are you talking about moving the differential pairs further from the edge of the board?
yes. but from what you're saying it's not possible anyway.
How far are the differential traces from board edge at present?
[…]
indeed. however i don't want to change the BOM, apart from anything that's a TI part not a "Well Known Easily Sourceable Part In The Shenzhen Huaqiang Road Eco-System".
dual rclamp0524's, one each side, it is.
I understand about part availability. For what it's worth, that document [SLLA324] concerns a TI part--TPD12S016 to be exact. It comes in both TSSOP and μQFN packages. The board layout we have been discussing in which they use the micro (type "D") connector they pair it with the μQFN package ESD part.
On Thu, Aug 17, 2017 at 12:01 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
ahhhh ok. i'm glad you're paying attention :)
I'm trying ;>)
:)
[…]
if i just take *out* the ground intermediary traces that would do the trick of bringing the impedance back up, is that right?
Should be a major step in the right direction.
what would you suggest, here - leave the intermediary GND traces in or take them out.
My suggestion here would be to remove the GND traces between differential pairs since we have established that we can't get 15mil clearance from the differential pair traces with the GND traces in place. We don't have enough room for that.
ok.
I would also look carefully at the GND traces separating the differential pairs from board edge and other circuitry. If we can't put 15mil between the differential pair traces and these GND traces, I would remove these GND traces as well. If we have to remove the GND traces between differential pairs and other circuitry, this will at least have the happy effect of providing 15mil spacing between the differential pair and that other circuitry.
flood-fill will just end up putting them back - i'd have to set a copper-to-trace separation @ 15mil as well.
there's one place where the diffpairs go past the main power line (IPSOUT) - that's got a 5 mil copper GND separating it at present: i'd be nervous about taking that out.
This is all based on the fact that we are using differential-mode transmission for the high-frequency HDMI signals.
also, i think i "Get It" about the intermediary wiggles. when the transmit end does automatic compensation that results in the signals coming out in such a way that, really, the inter-pair length-matching should be done from the *OPPOSITE* end i.e. from the CONNECTOR.
Maybe I misunderstood the standard because that wasn't my understanding. (All I know is second-hand because there are no freely available copies.) What I understood was:
- The receiver has the capability to recover up to 5 bit times of inter-pair skew,
o arse: *receiver* not transmitter.
Thus, in order to make an HDMI v1.4 standard-compliant transmitter (which is my understanding of what we are trying to do with the EOMA68-A20) we must emit from our HDMI connector an HDMI signal which exhibits max{T(inter-pair skew)} <= 0.2 * T(pixel) = 588ps This inter-pair skew can come from connector, the chip, and the PCB traces connecting them. It seems likely that the connector and the chip will likely be very minimal sources of inter-pair skew, and thus most, if not all, of the transmitter allocation falls to the PCB designer to use (or squander--depending on how you view it) in connecting the chip to the HDMI cable connector.
At the speed of propagation of signals in our microstrip differential pairs this amounts to max{length(inter-pair skew)} = v(propagation) * max{T(inter-pair skew)} = 150um/ps * 588ps = 88.2mm Toradex suggests we limit the inter-pair skew in the traces to 1/4 of that value or 0.5 * T(bit) which corresponds to a length of 22mm.
22 mm... okaaay.
From what I've seen, even without inter-pair skew compensation in the layout the inter-pair skew you observed was ~8mm < 22mm.
9. or so. okaaay now i get it.
If this is indeed how it works then I'll need to rethink my recommendations. (I outlined my understanding above.)
nono, my mistake.
Are you talking about moving the differential pairs further from the edge of the board?
yes. but from what you're saying it's not possible anyway.
How far are the differential traces from board edge at present?
0.9mm -> 35 mil.
to the nearest vias is 0.2mm -> 0.787mil
l.
2017-08-17 7:22 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Thu, Aug 17, 2017 at 12:01 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
I would also look carefully at the GND traces separating the differential pairs from board edge and other circuitry. If we can't put 15mil between the differential pair traces and these GND traces, I would remove these GND traces as well. If we have to remove the GND traces between differential pairs and other circuitry, this will at least have the happy effect of providing 15mil spacing between the differential pair and that other circuitry.
flood-fill will just end up putting them back - i'd have to set a copper-to-trace separation @ 15mil as well.
Isn't there a option to create barriers or free form where the floodfill may not come, white spaces so to speak. Seems to me there should be. You should be able to create "white" spots on the GND planes for various reasons.
On Thu, Aug 17, 2017 at 8:08 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
flood-fill will just end up putting them back - i'd have to set a copper-to-trace separation @ 15mil as well.
Isn't there a option to create barriers or free form where the floodfill may not come, white spaces so to speak. Seems to me there should be.
there is..... however that would mean having to maintain an exact and specific mirror of the exact path of the traces, whereby any changes *to* the exact and specific path of the traces would require a corresponding, exact, specific and precisely and without fail 100% matching change to that area.
total pain in the ass in other words.
... on the other hand simply changing *one parameter* in the design rules achieves the exact same result... done dynamically and with no fuss.
You should be able to create "white" spots on the GND planes for various reasons.
indeed.
On Aug 16, 2017, at 22:22, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Thu, Aug 17, 2017 at 12:01 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
[…] I would also look carefully at the GND traces separating the differential pairs from board edge and other circuitry. If we can't put 15mil between the differential pair traces and these GND traces, I would remove these GND traces as well. If we have to remove the GND traces between differential pairs and other circuitry, this will at least have the happy effect of providing 15mil spacing between the differential pair and that other circuitry.
flood-fill will just end up putting them back - i'd have to set a copper-to-trace separation @ 15mil as well.
Sounds like just the ticket. So you have a flood-fill on the bottom layer? Is the flood-fill connected to GND? Can you set the 15mil copper-to-trace separation as a property of the differential traces?
The goal with this 15mil clearance is to space other copper in the same plane far enough away to have a negligible effect on the differential impedance of the differential pair and by the same token negligible high-frequency signal coupling. The microstrip differential pair geometry is based on having ground plane (may it extend forever ;>) underneath the traces separated by a dielectric of thickness t. (We took that into account in the impedance calculations. Actually power and ground are identical from the perspective of high-frequency signals so we could have built our microstrip differential pair over a power plane--or even moved from one reference plane to another. If we change reference planes, then we need to provide a low-impedance at high frequency path for any return current. Since we used two different ground planes, plated through-hole vias work well. If we had used planes at different potentials we would couple through capacitors.)
there's one place where the diffpairs go past the main power line (IPSOUT) - that's got a 5 mil copper GND separating it at present: i'd be nervous about taking that out.
I wouldn't worry because that 5mil copper GND has 5mil spacing on each side, thus ensuring 15mil between the closest differential trace and power. That should be sufficient.
On the other hand, if I remember correctly the proximity to IPSOUT happened because we decided to do significant inter-pair skew compensation close to the power circuit. If we remove that inter-pair compensation, we may have enough space to keep that ground trace around IPSOUT and still make our 15mil clearance around the differential pairs.
The other thing that we can do if we have a little extra space after taking out the intermediary GND shield traces and inter-pair skew compensation wiggles is distribute the intra-pair skew compensation closer to the sources of intra-pair skew--corners. Right now you've done a great job of compensating for intra-pair skew in the first segment: from CPU lands to first via. Then there are some very significant wiggles when we first get to the bottom layer and I don't see any other intra-pair skew compensation all the way out to the connector.
If we can do it, the most effective place for intra-pair skew compensation is within 15mil of the skew source--right before or after a bend. If skew originates in a bend and is resolved by a complementary bend within 15mils, then we don't need to add anything specific.
If we distribute the intra-pair skew compensation as outlined above we will likely be able to accomplish it with some pretty small wiggles which may fit more easily into the available space.
[…]
- The receiver has the capability to recover up to 5 bit times of inter-pair skew,
o arse: *receiver* not transmitter.
No problem then. But it sure highlights the importance of having the correct perspective when thinking about the problem.:) (I have trouble with it too, at times. The right perspective often makes the problem much more tractable.)
[…]
Toradex suggests we limit the inter-pair skew in the traces to 1/4 of that value or 0.5 * T(bit) which corresponds to a length of 22mm.
22 mm... okaaay.
From what I've seen, even without inter-pair skew compensation in the layout the inter-pair skew you observed was ~8mm < 22mm.
- or so. okaaay now i get it.
You can see how I came to the conclusion that we will likely be fine without any inter-pair skew compensation--with even a pretty generous engineering margin.
Are you talking about moving the differential pairs further from the edge of the board?
yes. but from what you're saying it's not possible anyway.
How far are the differential traces from board edge at present?
0.9mm -> 35 mil.
to the nearest vias is 0.2mm -> 0.787mil
How far is the board-edge ground shield trace from the edge of the board? From the closest differential pair trace? How wide is the board-edge ground shield trace?
I'm guessing you meant the closest vias to the differential pair traces are 0.2mm = 7.87mil? Are these the ground-to-ground vias for low-impedance connection of reference planes? (Low-impedance return path close to signal vias?)
On Thu, Aug 17, 2017 at 5:20 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
flood-fill will just end up putting them back - i'd have to set a copper-to-trace separation @ 15mil as well.
Sounds like just the ticket. So you have a flood-fill on the bottom layer?
all layers.
Is the flood-fill connected to GND?
only when it's properly arranged to be so... i.e. when you don't you get a warning... short answer: yes.
Can you set the 15mil copper-to-trace separation as a property of the differential traces?
yyup. i really like PADS for this reason
The goal with this 15mil clearance is to space other copper in the same plane far enough away to have a negligible effect on the differential impedance of the differential pair and by the same token negligible high-frequency signal coupling.
okaaay. i get it.
The microstrip differential pair geometry is based on having ground plane (may it extend forever ;>)
:)
underneath the traces separated by a dielectric of thickness t. (We took that into account in the impedance calculations.
yehyeh.
Actually power and ground are identical from the perspective of high-frequency signals so we could have built our microstrip differential pair over a power plane--or even moved from one reference plane to another.
ohhh that explains why DDR3 has a big power-plane @ the 1/2 way "reference" voltage. nice.
there's one place where the diffpairs go past the main power line (IPSOUT) - that's got a 5 mil copper GND separating it at present: i'd be nervous about taking that out.
I wouldn't worry because that 5mil copper GND has 5mil spacing on each side, thus ensuring 15mil between the closest differential trace and power. That should be sufficient.
... need to check it.
On the other hand, if I remember correctly the proximity to IPSOUT happened because we decided to do significant inter-pair skew compensation close to the power circuit.
ah no: it's always been very close: in this revision i particularly wanted the vias left of the rclamp0524p to be reasonably symmetrical and clean, with a straight (diff-paired) path to the rclamp0524p instead of taking a turn to get to it (as in previous revisions).
that required a little bit more space, which meant moving IPSOUT's vias a little bit further over. i could _probably_ move them over a bit further...
The other thing that we can do if we have a little extra space after taking out the intermediary GND shield traces and inter-pair skew compensation wiggles is distribute the intra-pair skew compensation closer to the sources of intra-pair skew--corners.
aw poop - changing those is quite a task. there's some bugs due to a combination of grid snap and push-and-shove in PADS where removing the long straights means i can't add them back in again. and i need to remove them because otherwise i don't know how long the traces are from the vias. what i do is:
* remove the long sections * re-add a *short* diffpair section of only about 1mm * those end up being equal length * then because the traces aren't complete PADS will tell you exactly how long they are * therefore i can now measure them both and... * therefore i know exactly how much manual "wiggle" to put in the shorter one.
once the wiggles are done i can re-add the long sections, confident that the signals will be matched.
but it's a pain to do! :)
Right now you've done a great job of compensating for intra-pair skew in the first segment: from CPU lands to first via.
yehyeh. they're near-identical.
Then there are some very significant wiggles when we first get to the bottom layer
yes. intra-pair correction due to wanting to have the 1st layer traces all the same length. it's nearly... 1.5mm to correct, due to not just the offset of the vias but also the turn. if i tried to stagger those first vias the other way (which i tried once) then there's not enough room to have those 1st trace segments be equal length...
and I don't see any other intra-pair skew compensation all the way out to the connector.
that's because they're all fine... ok i read somewhere that it's ok to have some intra-pair skew on short lengths between turns. sooOo... i'm assuming that the critical part is the long straight. sooOOo i arranged for the wiggles to make perfect length-matching just as each pair hits the beginning of each long straight.
now (and i've removed the inter-pair skew in the current revision) what i *haven't* done is add in any inter-skew correction at the points marked in green (attached). i'm assuming that those diagonal cross-paths (between each green ring) are... within acceptable tolerance for intra-skew.
If we can do it, the most effective place for intra-pair skew compensation is within 15mil of the skew source--right before or after a bend. If skew originates in a bend and is resolved by a complementary bend within 15mils, then we don't need to add anything specific.
mmmm *grumble, grumble*.... i think there might be space to add them, around where the green rings are, by moving the diagonal pieces to the right a bit.
How far are the differential traces from board edge at present?
0.9mm -> 35 mil.
to the nearest vias is 0.2mm -> 0.787mil
How far is the board-edge ground shield trace from the edge of the board?
to the edge of the GND shield trace: 0.46mm -> 18 mil
From the closest differential pair trace?
to the edge of the CK diffpair, 0.93mm -> 36.6 mil
How wide is the board-edge ground shield trace?
pffh :) peanuts. very tight. 13 mil (that's to the vias as well, which i realise is slightly dodgy).
I'm guessing you meant the closest vias to the differential pair traces are 0.2mm = 7.87mil?
yyep.
Are these the ground-to-ground vias for low-impedance connection of reference planes? (Low-impedance return path close to signal vias?)
honestly i haven't been thinking in terms so specific: i just add them arbitrarily because i heard it was the right thing to do! learning fast...
l.
On Aug 18, 2017, at 19:54, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Thu, Aug 17, 2017 at 5:20 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
[…]
So you have a flood-fill on the bottom layer?
all layers.
Is the flood-fill connected to GND?
only when it's properly arranged to be so... i.e. when you don't you get a warning... short answer: yes.
Can you set the 15mil copper-to-trace separation as a property of the differential traces?
yyup. i really like PADS for this reason
The goal with this 15mil clearance is to space other copper in the same plane far enough away to have a negligible effect on the differential impedance of the differential pair and by the same token negligible high-frequency signal coupling.
okaaay. i get it.
The microstrip differential pair geometry is based on having ground plane (may it extend forever ;>)
:)
underneath the traces separated by a dielectric of thickness t. (We took that into account in the impedance calculations.
yehyeh.
Actually power and ground are identical from the perspective of high-frequency signals so we could have built our microstrip differential pair over a power plane--or even moved from one reference plane to another.
ohhh that explains why DDR3 has a big power-plane @ the 1/2 way "reference" voltage. nice.
there's one place where the diffpairs go past the main power line (IPSOUT) - that's got a 5 mil copper GND separating it at present: i'd be nervous about taking that out.
I wouldn't worry because that 5mil copper GND has 5mil spacing on each side, thus ensuring 15mil between the closest differential trace and power. That should be sufficient.
... need to check it.
On the other hand, if I remember correctly the proximity to IPSOUT happened because we decided to do significant inter-pair skew compensation close to the power circuit.
ah no: it's always been very close: in this revision i particularly wanted the vias left of the rclamp0524p to be reasonably symmetrical and clean, with a straight (diff-paired) path to the rclamp0524p instead of taking a turn to get to it (as in previous revisions).
that required a little bit more space, which meant moving IPSOUT's vias a little bit further over. i could _probably_ move them over a bit further...
The other thing that we can do if we have a little extra space after taking out the intermediary GND shield traces and inter-pair skew compensation wiggles is distribute the intra-pair skew compensation closer to the sources of intra-pair skew--corners.
aw poop - changing those is quite a task. there's some bugs due to a combination of grid snap and push-and-shove in PADS where removing the long straights means i can't add them back in again. and i need to remove them because otherwise i don't know how long the traces are from the vias. what i do is:
- remove the long sections
- re-add a *short* diffpair section of only about 1mm
- those end up being equal length
- then because the traces aren't complete PADS will tell you exactly
how long they are
- therefore i can now measure them both and...
- therefore i know exactly how much manual "wiggle" to put in the shorter one.
once the wiggles are done i can re-add the long sections, confident that the signals will be matched.
but it's a pain to do! :)
Right now you've done a great job of compensating for intra-pair skew in the first segment: from CPU lands to first via.
yehyeh. they're near-identical.
Then there are some very significant wiggles when we first get to the bottom layer
yes. intra-pair correction due to wanting to have the 1st layer traces all the same length. it's nearly... 1.5mm to correct, due to not just the offset of the vias but also the turn. if i tried to stagger those first vias the other way (which i tried once) then there's not enough room to have those 1st trace segments be equal length...
and I don't see any other intra-pair skew compensation all the way out to the connector.
that's because they're all fine... ok i read somewhere that it's ok to have some intra-pair skew on short lengths between turns. sooOo... i'm assuming that the critical part is the long straight. sooOOo i arranged for the wiggles to make perfect length-matching just as each pair hits the beginning of each long straight.
now (and i've removed the inter-pair skew in the current revision) what i *haven't* done is add in any inter-skew correction at the points marked in green (attached). i'm assuming that those diagonal cross-paths (between each green ring) are... within acceptable tolerance for intra-skew.
If we can do it, the most effective place for intra-pair skew compensation is within 15mil of the skew source--right before or after a bend. If skew originates in a bend and is resolved by a complementary bend within 15mils, then we don't need to add anything specific.
mmmm *grumble, grumble*.... i think there might be space to add them, around where the green rings are, by moving the diagonal pieces to the right a bit.
How far are the differential traces from board edge at present?
0.9mm -> 35 mil.
to the nearest vias is 0.2mm -> 0.787mil
How far is the board-edge ground shield trace from the edge of the board?
to the edge of the GND shield trace: 0.46mm -> 18 mil
From the closest differential pair trace?
to the edge of the CK diffpair, 0.93mm -> 36.6 mil
How wide is the board-edge ground shield trace?
pffh :) peanuts. very tight. 13 mil (that's to the vias as well, which i realise is slightly dodgy).
I'm guessing you meant the closest vias to the differential pair traces are 0.2mm = 7.87mil?
yyep.
Are these the ground-to-ground vias for low-impedance connection of reference planes? (Low-impedance return path close to signal vias?)
honestly i haven't been thinking in terms so specific: i just add them arbitrarily because i heard it was the right thing to do! learning fast...
l. <Untitled.jpg> _______________________________________________ arm-netbook mailing list arm-netbook@lists.phcomp.co.uk http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook Send large attachments to arm-netbook@files.phcomp.co.uk
whoops looks like you hit reply early, richard! :)
On Sat, Aug 19, 2017 at 3:07 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
<Untitled.jpg>
On Aug 19, 2017, at 07:30, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
whoops looks like you hit reply early, richard! :)
Yes! My apologies to everyone on the list. I am working on a more substantive reply but didn't get it finished or sent yesterday before I did several hours of driving (southeast from Seattle, Washington into northern Oregon). Today several more hours of driving to reach an area where we can observe the total solar eclipse tomorrow morning. (I'm on vacation with my family.)
On Sun, Aug 20, 2017 at 2:58 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
whoops looks like you hit reply early, richard! :)
Today several more hours of driving to reach an area where we can observe the total solar eclipse tomorrow morning. (I'm on vacation with my family.)
nice! yeh the lunar eclipse was... eclipsed by clouds here in taipei.
l.
On Aug 20, 2017, at 07:37, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
nice! yeh the lunar eclipse was... eclipsed by clouds here in taipei.
Sorry to hear that. My family saw a lunar eclipse several years ago and it was quiet and beautiful. It happened in the wee hours of the morning so my wife and I got the kids up, bundled them into the car and drove half a mile to a field where we had a great view. So I recommend it--if you can get the weather to cooperate! ;>)
On Aug 18, 2017, at 19:54, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Thu, Aug 17, 2017 at 5:20 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
So you have a flood-fill on the bottom layer?
all layers.
Is the flood-fill connected to GND?
only when it's properly arranged to be so... i.e. when you don't you get a warning... short answer: yes.
So it sounds to me like some of the ground vias can connect more than just layers 2 and 5 if they happen to coincide with ground flood-fill on one or more other layers?
Can you set the 15mil copper-to-trace separation as a property of the differential traces?
yyup. i really like PADS for this reason
Nice.
[…]
there's one place where the diffpairs go past the main power line (IPSOUT) - that's got a 5 mil copper GND separating it at present: i'd be nervous about taking that out.
I wouldn't worry because that 5mil copper GND has 5mil spacing on each side, thus ensuring 15mil between the closest differential trace and power. That should be sufficient.
... need to check it.
Those were my understanding of the limits of your board fabricator: min{spacing} = 5mil min{trace width} = 5mil
it's always been very close: in this revision i particularly wanted the vias left of the rclamp0524p to be reasonably symmetrical and clean, with a straight (diff-paired) path to the rclamp0524p instead of taking a turn to get to it (as in previous revisions).
that required a little bit more space, which meant moving IPSOUT's vias a little bit further over. i could _probably_ move them over a bit further...
Sounds fine.
The other thing that we can do if we have a little extra space after taking out the intermediary GND shield traces and inter-pair skew compensation wiggles is distribute the intra-pair skew compensation closer to the sources of intra-pair skew--corners.
aw poop - changing those is quite a task. there's some bugs due to a combination of grid snap and push-and-shove in PADS where removing the long straights means i can't add them back in again. and i need to remove them because otherwise i don't know how long the traces are from the vias. what i do is:
- remove the long sections
- re-add a *short* diffpair section of only about 1mm
- those end up being equal length
- then because the traces aren't complete PADS will tell you exactly
how long they are
- therefore i can now measure them both and...
- therefore i know exactly how much manual "wiggle" to put in the shorter one.
once the wiggles are done i can re-add the long sections, confident that the signals will be matched.
but it's a pain to do! :)
I'm glad you have a method that works. I'm sorry it is such a pain. Too bad it isn't more straightforward. Is PADS libre software? I ask because here's an itch.
Right now you've done a great job of compensating for intra-pair skew in the first segment: from CPU lands to first via.
yehyeh. they're near-identical.
Then there are some very significant wiggles when we first get to the bottom layer
yes. intra-pair correction due to wanting to have the 1st layer traces all the same length. it's nearly... 1.5mm to correct, due to not just the offset of the vias but also the turn. if i tried to stagger those first vias the other way (which i tried once) then there's not enough room to have those 1st trace segments be equal length...
and I don't see any other intra-pair skew compensation all the way out to the connector.
that's because they're all fine... ok i read somewhere that it's ok to have some intra-pair skew on short lengths between turns. sooOo... i'm assuming that the critical part is the long straight. sooOOo i arranged for the wiggles to make perfect length-matching just as each pair hits the beginning of each long straight.
now (and i've removed the inter-pair skew in the current revision) what i *haven't* done is add in any inter-skew correction at the points marked in green (attached). i'm assuming that those diagonal cross-paths (between each green ring) are... within acceptable tolerance for intra-skew.
If we can do it, the most effective place for intra-pair skew compensation is within 15mil of the skew source--right before or after a bend. If skew originates in a bend and is resolved by a complementary bend within 15mils, then we don't need to add anything specific.
mmmm *grumble, grumble*.... i think there might be space to add them, around where the green rings are, by moving the diagonal pieces to the right a bit.
Sounds like a good plan. How much intra-pair skew do we incur at each of those bends?
How far are the differential traces from board edge at present?
0.9mm -> 35 mil.
to the nearest vias is 0.2mm -> 0.787mil
How far is the board-edge ground shield trace from the edge of the board?
to the edge of the GND shield trace: 0.46mm -> 18 mil
From the closest differential pair trace?
to the edge of the CK diffpair, 0.93mm -> 36.6 mil
How wide is the board-edge ground shield trace?
pffh :) peanuts. very tight. 13 mil (that's to the vias as well, which i realise is slightly dodgy).
We'll take what we can fit.
I'm guessing you meant the closest vias to the differential pair traces are 0.2mm = 7.87mil?
yyep.
In order for me to understand better the dimensions you're quoting allow me to resort to a diagram.
edge of the world/board |<- spacing to first Cu ->| v |<-width of ground shield trace ->|<-spacing to diff. pair->|CLK- FR-4 substrateFR-4 substrateFR-4 substrateFR-4 substrateFR-4 substrate
Are these the ground-to-ground vias for low-impedance connection of reference planes? (Low-impedance return path close to signal vias?)
honestly i haven't been thinking in terms so specific: i just add them arbitrarily because i heard it was the right thing to do! learning fast...
It is good to have a scattering of vias connecting related planes (in this case ground). With limited space it becomes more important to use what heuristic we can muster to place them strategically.
(Writing from our tent here in John Day, Oregon. The total solar eclipse yesterday morning was spectacular. I'm glad we travelled to be in the path of totality. I've seen partial solar eclipses before but this was well worth the trip. We're going to visit the John Day Fossil Beds today before we head home tomorrow.)
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Tue, Aug 22, 2017 at 2:43 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Aug 18, 2017, at 19:54, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Thu, Aug 17, 2017 at 5:20 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
So you have a flood-fill on the bottom layer?
all layers.
Is the flood-fill connected to GND?
only when it's properly arranged to be so... i.e. when you don't you get a warning... short answer: yes.
So it sounds to me like some of the ground vias can connect more than just layers 2 and 5 if they happen to coincide with ground flood-fill on one or more other layers?
yehyeh, they go all the way through and connect to all layers 1 through 6 if there's flood-fill or a GND trace on any of them.
Those were my understanding of the limits of your board fabricator: min{spacing} = 5mil min{trace width} = 5mil
yeah it's more what i set so things don't get ridiculously expensive... but yes.
it's always been very close: in this revision i particularly wanted the vias left of the rclamp0524p to be reasonably symmetrical and clean, with a straight (diff-paired) path to the rclamp0524p instead of taking a turn to get to it (as in previous revisions).
that required a little bit more space, which meant moving IPSOUT's vias a little bit further over. i could _probably_ move them over a bit further...
Sounds fine.
The other thing that we can do if we have a little extra space after taking out the intermediary GND shield traces and inter-pair skew compensation wiggles is distribute the intra-pair skew compensation closer to the sources of intra-pair skew--corners.
aw poop - changing those is quite a task. there's some bugs due to a combination of grid snap and push-and-shove in PADS where removing the long straights means i can't add them back in again. and i need to remove them because otherwise i don't know how long the traces are from the vias. what i do is:
- remove the long sections
- re-add a *short* diffpair section of only about 1mm
- those end up being equal length
- then because the traces aren't complete PADS will tell you exactly
how long they are
- therefore i can now measure them both and...
- therefore i know exactly how much manual "wiggle" to put in the shorter one.
once the wiggles are done i can re-add the long sections, confident that the signals will be matched.
but it's a pain to do! :)
I'm glad you have a method that works. I'm sorry it is such a pain. Too bad it isn't more straightforward. Is PADS libre software? I ask because here's an itch.
Right now you've done a great job of compensating for intra-pair skew in the first segment: from CPU lands to first via.
yehyeh. they're near-identical.
Then there are some very significant wiggles when we first get to the bottom layer
yes. intra-pair correction due to wanting to have the 1st layer traces all the same length. it's nearly... 1.5mm to correct, due to not just the offset of the vias but also the turn. if i tried to stagger those first vias the other way (which i tried once) then there's not enough room to have those 1st trace segments be equal length...
and I don't see any other intra-pair skew compensation all the way out to the connector.
that's because they're all fine... ok i read somewhere that it's ok to have some intra-pair skew on short lengths between turns. sooOo... i'm assuming that the critical part is the long straight. sooOOo i arranged for the wiggles to make perfect length-matching just as each pair hits the beginning of each long straight.
now (and i've removed the inter-pair skew in the current revision) what i *haven't* done is add in any inter-skew correction at the points marked in green (attached). i'm assuming that those diagonal cross-paths (between each green ring) are... within acceptable tolerance for intra-skew.
If we can do it, the most effective place for intra-pair skew compensation is within 15mil of the skew source--right before or after a bend. If skew originates in a bend and is resolved by a complementary bend within 15mils, then we don't need to add anything specific.
mmmm *grumble, grumble*.... i think there might be space to add them, around where the green rings are, by moving the diagonal pieces to the right a bit.
Sounds like a good plan. How much intra-pair skew do we incur at each of those bends?
very little. it's a 45 degree bend in each case so.... can probably work out the maths... 15mil separation...
How far are the differential traces from board edge at present?
0.9mm -> 35 mil.
to the nearest vias is 0.2mm -> 0.787mil
How far is the board-edge ground shield trace from the edge of the board?
to the edge of the GND shield trace: 0.46mm -> 18 mil
From the closest differential pair trace?
to the edge of the CK diffpair, 0.93mm -> 36.6 mil
How wide is the board-edge ground shield trace?
pffh :) peanuts. very tight. 13 mil (that's to the vias as well, which i realise is slightly dodgy).
We'll take what we can fit.
I'm guessing you meant the closest vias to the differential pair traces are 0.2mm = 7.87mil?
yyep.
In order for me to understand better the dimensions you're quoting allow me to resort to a diagram.
edge of the world/board |<- spacing to first Cu ->| v |<-width of ground shield trace ->|<-spacing to diff. pair->|CLK- FR-4 substrateFR-4 substrateFR-4 substrateFR-4 substrateFR-4 substrate
urk. attached diagram is probably a lot easier. i also checked the Design Rules: board-to-everything-and-anything is set to 11.84 mil, everything-else-to-anything-else is set to 5mil.
so in the attached diagram those traces i put right at the bottom will be overwritten by about... 1.2 mil to make up to the 11.84 board-to-copper clearance.
so, actually very simple. everything-to-everything-but-board: 5mil. board-to-everything: 11.84mil.
(Writing from our tent here in John Day, Oregon. The total solar eclipse yesterday morning was spectacular. I'm glad we travelled to be in the path of totality. I've seen partial solar eclipses before but this was well worth the trip. We're going to visit the John Day Fossil Beds today before we head home tomorrow.)
niice :)
On Aug 22, 2017, at 07:13, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Tue, Aug 22, 2017 at 2:43 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Is PADS libre software? I ask because here's an itch.
I looked for myself and found PADS[*] is a product of Mentor Graphics. Looks like a nice tool, but I guess I don't have to worry about submitting a patch. ;>)
Reference: [*] https://www.pads.com/
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Sun, Aug 27, 2017 at 7:36 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Aug 22, 2017, at 07:13, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Tue, Aug 22, 2017 at 2:43 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Is PADS libre software? I ask because here's an itch.
I looked for myself and found PADS[*] is a product of Mentor Graphics.
yyep. absolutely awesome one, too. i'm recommending it constantly to people, not just in the libre world but also those who use proprietary tools as well. the learning curve is nowhere near as steep as with other proprietary tools. ORCAD is completely insane: 20 menus with over 30 options on each. totally user-hostile.
PADS: everything is context-sensitive, and the menu options show you a graphical representation (2D cutaway or overhead view) of what you just selected. absolutely superb.
Looks like a nice tool, but I guess I don't have to worry about submitting a patch. ;>)
love to... but ehhmmm.. no :)
l.
On Aug 22, 2017, at 08:13, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Tue, Aug 22, 2017 at 2:43 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
How much intra-pair skew do we incur at each of those bends?
very little. it's a 45 degree bend in each case so.... can probably work out the maths... 15mil separation...
Between traces of the same differential pair (intra-pair) I would have expected 5mil separation.
I'm not entirely sure how PADS does the trace length calculation: 1. Is it measuring the inside edges of the differential pair traces? Then the intra-pair skew from one 45° corner would be 5mil. 2. Is it measuring the centers of the 5mil wide traces? If so I'd expect the intra-pair skew to be 10mil. 3. It may be measuring in a different way of which I'm not thinking.
attached diagram is probably a lot easier. i also checked the Design Rules: board-to-everything-and-anything is set to 11.84 mil, everything-else-to-anything-else is set to 5mil.
so in the attached diagram those traces i put right at the bottom will be overwritten by about... 1.2 mil to make up to the 11.84 board-to-copper clearance.
Does that mean that flood fill will cover out from 13mil off the board edge (as noted in the diagram) up to the 11.84mil board-to-copper clearance?
so, actually very simple. everything-to-everything-but-board: 5mil. board-to-everything: 11.84mil.
Simple is good--only as complicated as it needs to be.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Mon, Aug 28, 2017 at 10:13 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Aug 22, 2017, at 08:13, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Tue, Aug 22, 2017 at 2:43 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
How much intra-pair skew do we incur at each of those bends?
very little. it's a 45 degree bend in each case so.... can probably work out the maths... 15mil separation...
Between traces of the same differential pair (intra-pair) I would have expected 5mil separation.
sorry i was referring to outer-edge to outer-edge so 5 trace + 5 gap + 5 tracee
I'm not entirely sure how PADS does the trace length calculation:
no idea. it's most likely to be down the middle.
- Is it measuring the centers of the 5mil wide traces? If so I'd expect the intra-pair skew to be 10mil.
true! this i would expect.
so in the attached diagram those traces i put right at the bottom will be overwritten by about... 1.2 mil to make up to the 11.84 board-to-copper clearance.
Does that mean that flood fill will cover out from 13mil off the board edge (as noted in the diagram) up to the 11.84mil board-to-copper clearance?
remember i mentioned that the flood-fill has some "curvature" rules on it: if the radius (a parameter somewhere) is too small the flood-fill won't go in there.
example attached: see green arrow, the track "jigs" in just at that point. grey is the flood outline btw. at that point the radius of the grey flood-fill just below the green arrow is too small, so the flood-fill refuses to go into the gap between the board edge and the track with the "jig" in it.
so instead what i have to do here is to make that "manual" GND track 11 or so mil wide, and that does the trick.
anyway *apart* from those special circumstances, what will happen in the case you refer to is that PADS will create a tiny bit of GND copper (13-11.84 = 1.16mm) wide just *below* that VIA's outer edge, including covering the via itself.
so.. yes! that's actually shown in the 2nd picture. i selected (highlighted) the VIA, and you can see how the flood-fill outline (grey) overlaps the entire VIA (outer extent of which is 13mm from the board edge) but the flood comes *no closer* than it is told to, which is 11.84mm.
basically the VIA - which is a GND via - is totally irrelevant to the distance / extent that the flood fill goes to the board edge. now if that VIA was NOT a part of the GND net *THEN* the flood fill would avoid THAT via (by the amount set in the Design Rules). but if it's the same net, flood fill "ignores" it in effect (and just floods over it as if it wasn't there).
l.
On Aug 22, 2017, at 08:13, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
Looking at your cool diagram from 22 Aug, the ground trace at the bottom of the board looks like it is 5mil wide as it appears the same width as HTXCN et al. That assumption together with the dimensions you provide leads me to believe that we can nearly have our cake and eat too! distance from ground trace to closest differential trace = 37mil from board edge to closest differential trace - 18mil from board edge to ground trace - 5mil ground trace width = 14mil
I notice that the via copper extends to 13mil from board edge. Thus, if we were to move the ground trace down 1mil, we would have 15mil spacing to the closest differential trace without breaking the 11.84mil board edge clearance. (Vias would extend to 12mil from board edge.)
This is good for impedance on the differential pair next to the board edge, HTXC = HDMI transmit clock. The vias will encroach closer. Can we trim the pad on the side towards the differential trace to reduce the encroachment?
2017-08-17 1:01 GMT+02:00 Richard Wilbur richard.wilbur@gmail.com:
On Aug 15, 2017, at 23:31, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
if i just take *out* the ground intermediary traces that would do the trick of bringing the impedance back up, is that right?
Should be a major step in the right direction.
How about the ground plane below the traces... That's a major stray capacitance and closer than the "narrow" surrounding GND traces?
On Thu, Aug 17, 2017 at 7:28 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
How about the ground plane below the traces... That's a major stray capacitance and closer than the "narrow" surrounding GND traces?
good question!
On Aug 16, 2017, at 23:28, "mike.valk@gmail.com" mike.valk@gmail.com wrote:
2017-08-17 1:01 GMT+02:00 Richard Wilbur richard.wilbur@gmail.com:
On Aug 15, 2017, at 23:31, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote: if i just take *out* the ground intermediary traces that would do the trick of bringing the impedance back up, is that right?
Should be a major step in the right direction.
How about the ground plane below the traces... That's a major stray capacitance and closer than the "narrow" surrounding GND traces?
The ground plane would be stray except we designed it into the single-ended and differential impedance. At this point it is integral to our differential microstrip geometry. (See my original post in the thread "HDMI High-Frequency Layout: Impedance".)
2017-08-17 18:30 GMT+02:00 Richard Wilbur richard.wilbur@gmail.com:
On Aug 16, 2017, at 23:28, "mike.valk@gmail.com" mike.valk@gmail.com wrote:
2017-08-17 1:01 GMT+02:00 Richard Wilbur richard.wilbur@gmail.com:
On Aug 15, 2017, at 23:31, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote: if i just take *out* the ground intermediary traces that would do the trick of bringing the impedance back up, is that right?
Should be a major step in the right direction.
After thinking it through I have to agree. Each GND trace would become coupled with the diff pairs. Effectively creating a link between two pairs. Which we do not want.
How about the ground plane below the traces... That's a major stray capacitance and closer than the "narrow" surrounding GND traces?
The ground plane would be stray except we designed it into the single-ended and differential impedance. At this point it is integral to our differential microstrip geometry. (See my original post in the thread "HDMI High-Frequency Layout: Impedance".)
I'll read that again.
I guess we just need to make sure that no other GND loop crosses the HDMI plane. Perhaps create a barrier on the GND that follows the outer HDMI traces. To prevent unwanted GND loops
On Aug 17, 2017, at 14:44, "mike.valk@gmail.com" mike.valk@gmail.com wrote:
I guess we just need to make sure that no other GND loop crosses the HDMI plane. Perhaps create a barrier on the GND that follows the outer HDMI traces. To prevent unwanted GND loops
(Thank you for the link to another interesting high-frequency circuit and PCB layout reference. It concentrates on analog circuits but still has good wisdom and recommendations.)
Since we are routing the highest speed signals as a differential pair, and to the extent that we are able to create a differential microstrip transmission line, our biggest return current will be through the neighboring trace of the differential pair.
Since our differential microstrip transmission line will not be perfect, we are using ground vias to provide a low-impedance path for return currents across changes in the associated ground plane.
You bring up an interesting point: what other current return paths are in the same vicinity? I have not analyzed that in any detail. At least there are no other lines from signal source to signal sink that I know of that cross the region of the board where the high-frequency HDMI signals are routed. Also, to my knowledge we don't have segmented or restricted ground planes that would isolate regions with a higher-impedance reference.
On Fri, Aug 18, 2017 at 5:51 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
You bring up an interesting point: what other current return paths are in the same vicinity? I have not analyzed that in any detail. At least there are no other lines from signal source to signal sink that I know of that cross the region of the board where the high-frequency HDMI signals are routed. Also, to my knowledge we don't have segmented or restricted ground planes that would isolate regions with a higher-impedance reference.
CEC etc. all follow roughly the same path, on layer 3 (separated by GND).
i just noticed that SD0 runs round the back of the HDMI 1st set of VIAS (with no GND separation) on layer 3 - i've removed the SATA power (not being used) so i can shift them up a bit
some GPIOs cross on layer 3 as well, just near the GND shielding near those first vias...
not much.
l.
On Aug 18, 2017, at 20:13, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Fri, Aug 18, 2017 at 5:51 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
You bring up an interesting point: what other current return paths are in the same vicinity? I have not analyzed that in any detail. At least there are no other lines from signal source to signal sink that I know of that cross the region of the board where the high-frequency HDMI signals are routed. Also, to my knowledge we don't have segmented or restricted ground planes that would isolate regions with a higher-impedance reference.
CEC etc. all follow roughly the same path, on layer 3 (separated by GND).
i just noticed that SD0 runs round the back of the HDMI 1st set of VIAS (with no GND separation) on layer 3 - i've removed the SATA power (not being used) so i can shift them up a bit
some GPIOs cross on layer 3 as well, just near the GND shielding near those first vias...
not much.
Layer 3 always has ground separation from layer 1 in the intervening ground plane on layer 2 and likewise from layer 6 by layers 4 and 5. So I'm not worried about those signals.
Regarding the SATA power: Is it an important part of providing a SATA interface? If so, I would suggest not limiting our options on this card. My understanding is that SATA is significantly more efficient for harddisk data interface than USB.
Regarding SD0: To what interface does it belong? What is the maximum data rate on this line?
On Tue, Aug 22, 2017 at 4:30 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Layer 3 always has ground separation from layer 1 in the intervening ground plane on layer 2 and likewise from layer 6 by layers 4 and 5. So I'm not worried about those signals.
ok great.
Regarding the SATA power: Is it an important part of providing a SATA interface? If so, I would suggest not limiting our options on this card. My understanding is that SATA is significantly more efficient for harddisk data interface than USB.
SATA was on a very preliminary version of EOMA68. it was cut a long time ago.
Regarding SD0: To what interface does it belong? What is the maximum data rate on this line?
MicroSD card reading (and other SD/MMC / SDIO compatible interfaces). i *think* it's a max datarate of 50mhz....
l.
okaay, wiggle-progress... 1st image is left end, i think CX and TX0 i can shorten even more, there's definitely plenty of space there, big gap.
2nd image, right end, this is where i've added intra-pair wiggles at the 45 degree bends. i can't get away with a proper 4-turn using 45 degrees, PADS goes "nope that's too short a trace, i'm gonna assume you want a straight line instead" - there's probably an option somewhere for that but i've not found it. alternatively i can add in a (curvy) accordion....
anyway those wiggles are done by hand, some of them aren't pretty but in mil those traces are now nearly all to within 0.01 mil. i cheat a little and have made some of the corners in places a very very tiny arc, where you get better fine-grain control over the amount it takes off.
HTXCN just before the diff-pair vias at the end i'm a little concerned about, it looks a bit too... sharp-angled to make me feel totally comfortable... not a lot of space... i tried a single wiggle and it went too far away from HTXCP for me to feel happy about it.... put in two much smaller wiggles instead...
GND i'll remove as the absolute last thing.
l.
damn. i just noticed: the via transition here is at 90 degrees. i've been switching off except 1 layer at a time so didn't notice. arse.
i'll need to shift all but the TX2 via set down a fixed amount so i can get a second wiggle in the right-hand one one layer 1, to make the track come in to the top right corner (1 o clock). rather than as they do now: from right side (3 o clock).
TX2 i'll have to move to the right somewhat...
On Wed, Aug 23, 2017 at 5:27 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
damn. i just noticed: the via transition here is at 90 degrees. i've been switching off except 1 layer at a time so didn't notice. arse.
i'll need to shift all but the TX2 via set down a fixed amount so i can get a second wiggle in the right-hand one one layer 1, to make the track come in to the top right corner (1 o clock). rather than as they do now: from right side (3 o clock).
Not necessarily bad on the same scale as you might think. Our board is ~47mil thick while the copper is ~1mil thick, so when a signal plunges into a via from top to bottom it's already making a 90 degree turn into and out of the via.
I'm not criticizing your attempt to straighten out some corners we have control over in the signal path, just pointing out that vias themselves present the signal with a couple 90 degree turns.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Wed, Aug 30, 2017 at 9:34 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Wed, Aug 23, 2017 at 5:27 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
damn. i just noticed: the via transition here is at 90 degrees. i've been switching off except 1 layer at a time so didn't notice. arse.
i'll need to shift all but the TX2 via set down a fixed amount so i can get a second wiggle in the right-hand one one layer 1, to make the track come in to the top right corner (1 o clock). rather than as they do now: from right side (3 o clock).
Not necessarily bad on the same scale as you might think. Our board is ~47mil thick while the copper is ~1mil thick, so when a signal plunges into a via from top to bottom it's already making a 90 degree turn into and out of the via.
I'm not criticizing your attempt to straighten out some corners we have control over in the signal path, just pointing out that vias themselves present the signal with a couple 90 degree turns.
understood. which would be why they're best minimised and you're also supposed to keep them as close together as possible.
i did however hear somewhere that it's really really bad to make via tracks turn 180 back on themselves, and in the same vein it makes sense not to turn them too much other than being a sort-of "continuation" of "as if" they were on the same layer...
thx about the other responses.
l.
On Aug 22, 2017, at 12:25, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
okaay, wiggle-progress... 1st image is left end, i think CX and TX0 i can shorten even more, there's definitely plenty of space there, big gap.
Do you mean left end from the top of the board? (The first image I see shows the μHDMI connector end of the differential pairs.)
2nd image, right end, this is where i've added intra-pair wiggles at the 45 degree bends.
Do you mean right end from the top of the board? (The second image I see shows the SoC end of the HDMI differential pairs.)
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Tue, Aug 29, 2017 at 7:12 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Aug 22, 2017, at 12:25, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
okaay, wiggle-progress... 1st image is left end, i think CX and TX0 i can shorten even more, there's definitely plenty of space there, big gap.
Do you mean left end from the top of the board? (The first image I see shows the μHDMI connector end of the differential pairs.)
micro-hdmi connector is right end.
2nd image, right end, this is where i've added intra-pair wiggles at the 45 degree bends.
Do you mean right end from the top of the board? (The second image I see shows the SoC end of the HDMI differential pairs.)
SoC end of the HDMI traces is left end.
so.
http://lists.phcomp.co.uk/pipermail/arm-netbook/2017-August/014639.html
this is right end: http://lists.phcomp.co.uk/pipermail/arm-netbook/attachments/20170822/a4632db...
this is left end: http://lists.phcomp.co.uk/pipermail/arm-netbook/attachments/20170822/a4632db...
so.
okaay, wiggle-progress... 1st image is left end, i think CX and TX0 i can shorten even more, there's definitely plenty of space there, big gap.
http://lists.phcomp.co.uk/pipermail/arm-netbook/attachments/20170822/a4632db...
2nd image, right end, this is where i've added intra-pair wiggles at the 45 degree bends.
http://lists.phcomp.co.uk/pipermail/arm-netbook/attachments/20170822/a4632db...
l.
Luke,
Thank you ever so much for the clarification regarding perspective.
Comments inline below.
On Aug 22, 2017, at 12:25, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
okaay, wiggle-progress... 1st image is left end, i think CX and TX0 i can shorten even more, there's definitely plenty of space there, big gap.
Shortening CX and TX0 is fine but I would cramp any of the clearances to make it happen. On the other hand, if you were to put them into a 45° bend from south to southeast a little sooner, we would probably have enough room to adjust the ground shield trace on the southwest and west to abide by our 15mil differential trace to "anything not in the same pair" clearance (specifically to HTXCN).
2nd image, right end, this is where i've added intra-pair wiggles at the 45 degree bends. i can't get away with a proper 4-turn using 45 degrees, PADS goes "nope that's too short a trace, i'm gonna assume you want a straight line instead" - there's probably an option somewhere for that but i've not found it. alternatively i can add in a (curvy) accordion....
I agree. If you don't have enough room to make a trace facet length >= 1.5 * trace width then I would also resort to an arc (curve). (Which for 5mil wide traces suggests minimum facet length of 7.5mil.)
anyway those wiggles are done by hand, some of them aren't pretty but in mil those traces are now nearly all to within 0.01 mil. i cheat a little and have made some of the corners in places a very very tiny arc, where you get better fine-grain control over the amount it takes off.
Well done.
HTXCN just before the diff-pair vias at the end i'm a little concerned about, it looks a bit too... sharp-angled to make me feel totally comfortable... not a lot of space... i tried a single wiggle and it went too far away from HTXCP for me to feel happy about it.... put in two much smaller wiggles instead...
GND i'll remove as the absolute last thing.
Sounds great. Only really want to remove the ground traces that can't comply with the 15mil clearance between differential pair and anything not in the same pair.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Wed, Aug 30, 2017 at 1:54 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
Luke,
Thank you ever so much for the clarification regarding perspective.
Comments inline below.
On Aug 22, 2017, at 12:25, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
okaay, wiggle-progress... 1st image is left end, i think CX and TX0 i can shorten even more, there's definitely plenty of space there, big gap.
Shortening CX and TX0 is fine but I would cramp any of the clearances to make it happen.
there aren't any!! the GND separation vias see to that (attached). no there's not enough room to move those GND vias *in between* the VIAs, they need to be below, unfortunately. that means the diffpairs need to curve _round_ them (to the SW slightly). oops.
actually it just occurred to me that i could move the HXT?P vias over by another.... 10-15 mil or so, which would mean that the corresponding HXT?N traces would be able to go straight (directly south) instead of SW, S then SE.
phrrrrddhh :)
On the other hand, if you were to put them into a 45° bend from south to southeast a little sooner, we would probably have enough room to adjust the ground shield trace on the southwest and west to abide by our 15mil differential trace to "anything not in the same pair" clearance (specifically to HTXCN).
well, unless i add a flood-exclusion zone (thoughts on that?) anything W or SW of HTXCN is going to get flood-filled with GND.
or... i _could_ just put in a copper-to-diffpair Design Rule of "15 mil" clearance - that would keep the flood-fill away.
anyway those wiggles are done by hand, some of them aren't pretty but in mil those traces are now nearly all to within 0.01 mil. i cheat a little and have made some of the corners in places a very very tiny arc, where you get better fine-grain control over the amount it takes off.
Well done.
... i'm getting used to it....
HTXCN just before the diff-pair vias at the end i'm a little concerned about, it looks a bit too... sharp-angled to make me feel totally comfortable... not a lot of space... i tried a single wiggle and it went too far away from HTXCP for me to feel happy about it.... put in two much smaller wiggles instead...
GND i'll remove as the absolute last thing.
Sounds great. Only really want to remove the ground traces that can't comply with the 15mil clearance between differential pair and anything not in the same pair.
marked in this image, i was planning to remove the GND traces that are marked with red dots.... but only after all's done because currently they help keep the inter-pair separation.
does that sound sensible?
l.
Sent from my iPhone On Aug 29, 2017, at 19:13, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Wed, Aug 30, 2017 at 1:54 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
there aren't any!! the GND separation vias see to that (attached). no there's not enough room to move those GND vias *in between* the VIAs, they need to be below, unfortunately. that means the diffpairs need to curve _round_ them (to the SW slightly). oops.
actually it just occurred to me that i could move the HXT?P vias over by another.... 10-15 mil or so, which would mean that the corresponding HXT?N traces would be able to go straight (directly south) instead of SW, S then SE.
Which is an elegant way of doing some intra-pair (within the pair) skew compensation--by avoiding some the sources of skew to begin with. Sounds like a fine idea!
On the other hand, if you were to put them into a 45° bend from south to southeast a little sooner, we would probably have enough room to adjust the ground shield trace on the southwest and west to abide by our 15mil differential trace to "anything not in the same pair" clearance (specifically to HTXCN).
well, unless i add a flood-exclusion zone (thoughts on that?) anything W or SW of HTXCN is going to get flood-filled with GND.
Flood-exclusion zone is just the ticket if you don't have a more flexible way. In this case it would increase the maintenance costs (time and effort) of the differential pair clearance to other circuits because it has to be manually checked and moved when needed.
or... i _could_ just put in a copper-to-diffpair Design Rule of "15 mil" clearance - that would keep the flood-fill away.
I think this is the most maintainable solution.
[…]
... i'm getting used to it....
"Practice makes easy."
[…]
marked in this image, i was planning to remove the GND traces that are marked with red dots.... but only after all's done because currently they help keep the inter-pair separation.
does that sound sensible?
Eminently so!
On Wed, Aug 30, 2017 at 7:18 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
actually it just occurred to me that i could move the HXT?P vias over by another.... 10-15 mil or so, which would mean that the corresponding HXT?N traces would be able to go straight (directly south) instead of SW, S then SE.
Which is an elegant way of doing some intra-pair (within the pair) skew compensation--by avoiding some the sources of skew to begin with. Sounds like a fine idea!
mrhm grumble i have to redo those nice length-matchings.... agaaainn aaargh :)
or... i _could_ just put in a copper-to-diffpair Design Rule of "15 mil" clearance - that would keep the flood-fill away.
I think this is the most maintainable solution.
ok attached is the result of doing that. layer 1 just after the SoC the "surround" on the vias is well over 15mil away, on *all* layers... including GND. all VIAs are now avoided by the specified 15mil.
... seems a bit much, to me....
[…]
... i'm getting used to it....
"Practice makes easy."
[…]
marked in this image, i was planning to remove the GND traces that are marked with red dots.... but only after all's done because currently they help keep the inter-pair separation.
does that sound sensible?
Eminently so!
awesome.
On Wed, Aug 30, 2017 at 4:01 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Wed, Aug 30, 2017 at 7:18 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
[...]
mrhm grumble i have to redo those nice length-matchings.... agaaainn aaargh :)
I feel your pain. (I don't know whether this helps, but I've heard it is for a good cause.;>)
or... i _could_ just put in a copper-to-diffpair Design Rule of "15 mil" clearance - that would keep the flood-fill away.
I think this is the most maintainable solution.
ok attached is the result of doing that. layer 1 just after the SoC the "surround" on the vias is well over 15mil away, on *all* layers... including GND. all VIAs are now avoided by the specified 15mil.
... seems a bit much, to me....
This is an attempt to maintain the impedance of the differential pairs to ground which helps reduce the common mode signal (which will radiate as EMI). With re-reading I noticed that the same document from TI ("HDMI Design Guide") which recommends the clearance between differential traces and any copper not a part of that same differential pair be d >= 3s [1] also mentions in the summary of routing guidelines some geometry recommendations among which is d > 2s [2]. In doing some more reading on the subject, a TI High-Frequency Analog design seminar slide mentions that it is common to put ground planes along both sides of the microstrip differential pair but at a larger distance than we have room to accommodate.(width > spacing, d > 2w)[3]
I believe we can abide by all of these constraints at d = 3s. Thus my recommendation to move ground shields on the outside of the pairs to 15mil away from the closest pair and remove the ground shields between the pairs because that will constitute 15mil spacing between pairs.
The seminar notes also suggest vias tying the ground in the signal layer to the ground plane below the differential pair at least every 100mil along the signal path--quite a fence[3]. Obviously, we have to accommodate the signals on other layers, as well.
The images as I received them were named: received saved as ----------- ------------- Untitled3.jpg eoma68_a20_275b_connector_bot.jpg Untitled2.jpg eoma68_a20_275b_processor_top.jpg Untitled1.jpg eoma68_a20_275b_processor_bot.jpg Untitled4.jpg eoma68_a20_275b_processor_gnd.jpg
What I notice in eoma68_a20_275b_connector_bot.jpg is that the ground shield traces and ground vias which violate the 15mil differential-pair-to-anything-else clearance stick out noticeably from the ground fill. For the vias on the edge of the ground fill, one possible solution would be to sneak them back inside the ground fill. For ground vias that we need to be closer to the differential pair traces or shouldn't move for other reasons (lack of space), can we remove the via pad on the layer where they violate the clearance (in this case layer 6)? That would minimize the coupling without changing the connection between other ground layers.
In eoma68_a20_275b_processor_top.jpg, what I see looks good. I like the curves on XN traces and angles on XP since the curves minimize length to make a turn this also reduces the amount of intra-pair skew (and thus how much compensation is required). I notice HTX2N didn't get the same treatment. Is that because HTX2P makes an extra turn on its way to the via?
In regard to eoma68_a20_275b_processor_bot.jpg I notice that Toradex mentions spacing of parallel traces containing the same signal should be >= 4 * trace width.[4] (For us that would be 4*5mil = 20mil.) Thus all their pictures of intra-pair skew compensation don't have parallel sections (unless they are very short like the tricks in figure 31[5]): _ _ _ _/ _/
or _ _ _/ _/ _
instead of _ _ \ / | | <---parallel sections of same signal _/
They reserve parallel sections of same signal for large meanders involved in inter-pair (between pairs) skew compensation.
I would try and move the bottom ground shield trace (and associated fence vias) down 1mil so that the trace attains the 15mil clearance with HTXCN.
Again, the ground vias and ground shield traces that are closer than 15mil to differential traces and can be moved to respect that boundary would help improve the symmetry and keep the impedance up.
Specifically, the ground shield trace just north of the signal vias which land the signals on layer 6, could move up parallel with the north edge of the adjacent ground fill. Likewise the ground shield trace on the west side of HTXCN could move even with the edge of the ground fill on that side.
My name for eoma68_a20_275b_processor_gnd.jpg is a hypothesis as to what I guess this is a picture of--one of the ground planes over the top layer adjacent to the processor where the signal vias carry the signal from top to bottom. Is that a correct hypothesis?
The keep outs look good from a signal impedance standpoint. It looks like there is no pad on this layer (ground?) on the vias and the 15mil clearance rule is having the expected effect. What did this part of this layer look like before we instituted the 15mil clearance rule? What clearance did we have before? Specifically, did we already have a hole extending over all the signal vias' keep outs or were there fingers of ground that made it between (preferably connecting north to south)?
I don't especially like making such a large hole in the ground plane. If it were only one of two ground planes with that hole I wouldn't worry about it at all. This is both planes plus the power plane. So let's consider it for a moment. Please correct any errors of fact or perspective, below. 1. Each HDMI differential signal via is composed of a 6mil diameter plated-through hole and pads on appropriate layers. 2. The clearance imposes a 15mil radius around the hole = 36mil void in non-signal layer. (This then happens in power and both ground planes.) 3. The return current (from common mode signal) wants to follow the signal in relatively low impedance back to the signal source/driver which implies a power or ground pin of the driver close to the signal pin. Where are the power and ground pins on the SoC relative to the HDMI signal pins? Does the SoC have both positive and negative supply connections (e.g. +3.3V, -3.3V)? Are any of the pins suggestively named such as: VHDMI+, VHDMI- or VDIFF+, VDIFF-? 4. The return current will detour as needed (but it raises the impedance of the path). Probably want to keep the detours down to ~200mil. 5. Where on ground and power planes is the power flow most apparent? (Are we blocking the direct path for any high-power flow? Where are the power sources?[voltage convertors/regulators] Where are the power sinks?[users of power: SoC, etc.])
References:
[1] TI HDMI, p. 5.2 [2] TI HDMI, p. 8, #10 [3] TI Analog, p. 14, beware: they label dimensions differently [4] Toradex, page 17, section 6.2 [5] Toradex, page 25, figure 31
Bibliography:
Texas Instruments (TI HDMI): "HDMI Design Guide", High-Speed Interface Products, June 2007, http://e2e.ti.com/cfs-file/__key/telligent-evolution-components-attachments/...
Texas Instruments (TI Analog): "Section 5: High Speed PCB Layout Techniques", High Speed Analog Design and Application Seminar, Date?, http://www.ti.com/lit/ml/slyp173/slyp173.pdf
Toradex: "Layout Design Guide", v1.0, 14 April 2015, http://docs.toradex.com/102492-layout-design-guide.pdf
http://rhombus-tech.net/allwinner_a10/news/
ok so after the successful DC3 test this is the last final check before sending the gerbers off to the factory for pre-production prototyping. in the end i used a "keepout" area on both layers 1 and 3, drawn by hand, to ensure that no GND flooding gets near the HDMI traces on layers 1 and 6. l'm including layer 3 as an example of how the group of HDMI vias that come just out of the A20 punch a large hole: GND-flooded layers 2 and 5 as well as 4 (power plane) will also look like that.
richard if you want to zoom in on those pictures you should be able to click on them in a browser, then expand them: they're actually around 2,500 pixels wide, i just asked them to be displayed in that HTML page as only 1024 otherwise they wouldn't fit :)
you can see i removed the GND traces in between, and generally kept everything except VIAs away from them. it's not perfect but thanks to your help i'm pretty happy with it. if there's nothing major i want to send this off.
l.
On Sat, Sep 16, 2017 at 8:23 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
http://rhombus-tech.net/allwinner_a10/news/
ok so after the successful DC3 test this is the last final check before sending the gerbers off to the factory for pre-production prototyping.
3*Cheer!
in the end i used a "keepout" area on both layers 1 and 3, drawn by hand, to ensure that no GND flooding gets near the HDMI traces on layers 1 and 6.
"keepout" on layers 1 and 6, right? Not a bad idea, especially since it allows the situations at both ends of the traces to avoid design rule check (DRC) failures because we have copper that has to be closer than 15mil there.
l'm including layer 3 as an example of how the group of HDMI vias that come just out of the A20 punch a large hole: GND-flooded layers 2 and 5 as well as 4 (power plane) will also look like that.
Could you put a similar snapshot of layers 2, 4, 5 on hands.com (or wherever you think appropriate)? I'm interested to see what holes/voids and connections the power and ground planes have.
What are the names of the power pins on the A20? What voltages do you supply it? (Are any of them Vdiff+/-, e.g?) I'm interested in tracking down the power supply pins for the differential HDMI signals as that is where our return path for common-mode signal has to go.
I've read a little (not nearly as much as I'd like, but I lack time) about using a taper to match impedance differences while minimizing the reflection coefficient.[*] I'm thinking we can use it at both ends of this layout to great advantage. We taper from 5mil clearance around the A20 on layer 1 to 15mil clearance on layer 6. Later we taper from 15mil clearance to whatever the closest copper is at the ESD and connector lands.
Is the closest copper on layer 1, around the A20, 5mil from the HDMI differential signals?
What is the distance to the closest copper to the HDMI signals at the ESD lands?
What is the distance to the closest copper to the HDMI signals at the connector lands?
(I'm guessing in both cases it is likely the neighbouring lands. Is that correct?)
What is the minimum frequency we will be running the HDMI at? (With version 1.4 the highest clock is 340MHz which implies 3.4GHz data rate on each data line. Thus I would expect good edges if we design for harmonics of 34GHz.;>)
What is the vertical distance from layer to layer in our board stack?
The idea is we can taper the keepouts on our signal vias near the A20 by the layer and avoid such an abrupt change from layer 1 to layer 6.
Likewise, we can change the geometry of the keepout as we approach the ESD lands and finally the connector to likewise ease the transition.
richard if you want to zoom in on those pictures you should be able to click on them in a browser, then expand them: they're actually around 2,500 pixels wide, i just asked them to be displayed in that HTML page as only 1024 otherwise they wouldn't fit :)
Thank you. I am enjoying the views you posted.
you can see i removed the GND traces in between, and generally kept everything except VIAs away from them. it's not perfect but thanks to your help i'm pretty happy with it. if there's nothing major i want to send this off.
There is one place in layer 6 where the space between the CLK pair and the adjacent data pair looks like it exceeds 35mil for a non-trivial distance. I think we could safely reintroduce a ground trace connecting the 2 or 3 vias in that space and thus keep the environment close to 15mil from differential trace to either ground or neighbouring signal.
I'm not sure which of the gray dots are vias and which are not. Some of the vias might be able to sneak back into the ground-fill (out of the 15mil differential line clearance).
Reference:
[*] https://electronics.stackexchange.com/questions/84098/a-transmission-line-wi... https://www.microwaves101.com/encyclopedias/klopfenstein-taper
On Tue, Sep 19, 2017 at 11:26 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Sat, Sep 16, 2017 at 8:23 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
http://rhombus-tech.net/allwinner_a10/news/
ok so after the successful DC3 test this is the last final check before sending the gerbers off to the factory for pre-production prototyping.
3*Cheer!
:)
in the end i used a "keepout" area on both layers 1 and 3, drawn by hand, to ensure that no GND flooding gets near the HDMI traces on layers 1 and 6.
"keepout" on layers 1 and 6, right?
yehyeh. only where needed. not "cut-through to all layers"
Not a bad idea, especially since it allows the situations at both ends of the traces to avoid design rule check (DRC) failures because we have copper that has to be closer than 15mil there.
yehyeh
l'm including layer 3 as an example of how the group of HDMI vias that come just out of the A20 punch a large hole: GND-flooded layers 2 and 5 as well as 4 (power plane) will also look like that.
Could you put a similar snapshot of layers 2, 4, 5 on hands.com (or wherever you think appropriate)?
they're exactly the same as what you see for layer 3.... except entirely full. ok that's not actually true (i just checked) - do a page-refresh on the URL i just added layer 4 image)
I'm interested to see what holes/voids and connections the power and ground planes have.
there are *no* connections on the GND planes. the power plane (and GND layers) interestingly have done a full surround on the HDMI vias. remember i had to separate them by an unusual distance.
What are the names of the power pins on the A20? What voltages do you supply it?
1.1, 1.25, 2.5 and 3.3v.
(Are any of them Vdiff+/-, e.g?)
no.
I'm interested in tracking down the power supply pins for the differential HDMI signals as that is where our return path for common-mode signal has to go.
there's no specific power pin for HDMI. the GND pins are grouped in with a whole stack of other GND pins, there's absolutely no way it's practical to get a special GND plane to it: the board is extremely full already.
I've read a little (not nearly as much as I'd like, but I lack time) about using a taper to match impedance differences while minimizing the reflection coefficient.[*] I'm thinking we can use it at both ends of this layout to great advantage. We taper from 5mil clearance around the A20 on layer 1 to 15mil clearance on layer 6. Later we taper from 15mil clearance to whatever the closest copper is at the ESD and connector lands.
that's something that it would be helpful to have a rough diagram, even if it's hand-drawn [but see below: i think i understand it]
Is the closest copper on layer 1, around the A20, 5mil from the HDMI differential signals?
yes. everything's 5 mil design rule.
What is the distance to the closest copper to the HDMI signals at the ESD lands?
5 mil
What is the distance to the closest copper to the HDMI signals at the connector lands?
5 mil
(I'm guessing in both cases it is likely the neighbouring lands. Is that correct?)
What is the minimum frequency we will be running the HDMI at? (With version 1.4 the highest clock is 340MHz which implies 3.4GHz data rate on each data line. Thus I would expect good edges if we design for harmonics of 34GHz.;>)
:) 1920x1080p60. honestly though if it works at 1280x720p60 i'll be happy.
What is the vertical distance from layer to layer in our board stack?
it's a 6 layer 1.2mm PCB. if i have actually set the design parameters right (rather than just telling the factory manually) then the substrates are 1.35mil and the dielectrics 10mil
The idea is we can taper the keepouts on our signal vias near the A20 by the layer and avoid such an abrupt change from layer 1 to layer 6.
i would very much like to have used layer 3 instead of layer 6 for the HDMI signals long straightaway but it is too late now
Likewise, we can change the geometry of the keepout as we approach the ESD lands and finally the connector to likewise ease the transition.
okaaaay i think i understand what you mean.
richard if you want to zoom in on those pictures you should be able to click on them in a browser, then expand them: they're actually around 2,500 pixels wide, i just asked them to be displayed in that HTML page as only 1024 otherwise they wouldn't fit :)
Thank you. I am enjoying the views you posted.
:)
you can see i removed the GND traces in between, and generally kept everything except VIAs away from them. it's not perfect but thanks to your help i'm pretty happy with it. if there's nothing major i want to send this off.
There is one place in layer 6 where the space between the CLK pair and the adjacent data pair looks like it exceeds 35mil for a non-trivial distance. I think we could safely reintroduce a ground trace connecting the 2 or 3 vias in that space and thus keep the environment close to 15mil from differential trace to either ground or neighbouring signal.
good call. i know exactly where you mean. refresh URL and see new image.
http://rhombus-tech.net/allwinner_a10/news/
ok i did the taper at the DC3 connector end, and i think i got it reasonably ok at the A20 end. haven't run flood-fill. A20 end is a bit of a mess, bit unavoidable. left side is ok. right side... because of the immediate turn and the TX2 line...
I'm not sure which of the gray dots are vias and which are not. Some of the vias might be able to sneak back into the ground-fill (out of the 15mil differential line clearance).
they're all vias with the exception of the 2 we previously identified as being "centre of component indicator". which.... i don't believe are actually in the images because i specifically selected "one and only one layer" in each.
you probably saw those dots because previous images included "all layers". the dots are on... some special layers, don't know which ones.
ok.
so. i really want to wrap this up, and get the gerbers out.
loootta work... :)
l.
On Wed, Sep 20, 2017 at 1:57 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Tue, Sep 19, 2017 at 11:26 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Sat, Sep 16, 2017 at 8:23 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
[...]
l'm including layer 3 as an example of how the group of HDMI vias that come just out of the A20 punch a large hole: GND-flooded layers 2 and 5 as well as 4 (power plane) will also look like that.
Could you put a similar snapshot of layers 2, 4, 5 on hands.com (or wherever you think appropriate)?
they're exactly the same as what you see for layer 3.... except entirely full. ok that's not actually true (i just checked) - do a page-refresh on the URL i just added layer 4 image)
Thanks for the image.
I'm interested to see what holes/voids and connections the power and ground planes have.
there are *no* connections on the GND planes. the power plane (and GND layers) interestingly have done a full surround on the HDMI vias. remember i had to separate them by an unusual distance.
What clearance to the fill do you have on the HDMI differential signal vias on layer 3, as opposed to 2, 4, and 5? I see it leaves a void on layer 3 but not on layer 4 (or presumably 2 or 5).
What are the names of the power pins on the A20? What voltages do you supply it?
1.1, 1.25, 2.5 and 3.3v.
(Are any of them Vdiff+/-, e.g?)
no.
Good to know. Thanks.
I'm interested in tracking down the power supply pins for the differential HDMI signals as that is where our return path for common-mode signal has to go.
there's no specific power pin for HDMI. the GND pins are grouped in with a whole stack of other GND pins, there's absolutely no way it's practical to get a special GND plane to it: the board is extremely full already.
I'm not looking to provide any special connection to the power or ground pins. I just want to make sure we don't obstruct the return current path any more than necessary on its way from bottom reference ground plane (layer 5) to top reference ground plane (layer 2) to the power supply pins of the differential drivers: 1. ground plane (layer 2) via to SoC ground pin land (layer 1) 2. ground plane (layer 2) via to power supply decoupling capacitor ground land (layer 1), through decoupling capacitor to land on power supply trace (layer 1), through trace to SoC power supply pin land (layer 1).
The goal is to avoid unnecessarily impeding this return current path. I'm trying to avoid making the path >~200mil and putting any major obstruction (like a huge layer void) in the way.
I've read a little (not nearly as much as I'd like, but I lack time) about using a taper to match impedance differences while minimizing the reflection coefficient.[*] I'm thinking we can use it at both ends of this layout to great advantage. We taper from 5mil clearance around the A20 on layer 1 to 15mil clearance on layer 6. Later we taper from 15mil clearance to whatever the closest copper is at the ESD and connector lands.
that's something that it would be helpful to have a rough diagram, even if it's hand-drawn [but see below: i think i understand it]
Once I figure out the frequency => characteristic taper length situation I'll try to send a drawing and/or image. In the meantime I've been looking at [*].
Is the closest copper on layer 1, around the A20, 5mil from the HDMI differential signals?
yes. everything's 5 mil design rule.
What is the distance to the closest copper to the HDMI signals at the ESD lands?
5 mil
What is the distance to the closest copper to the HDMI signals at the connector lands?
5 mil
(I'm guessing in both cases it is likely the neighbouring lands. Is that correct?)
In retrospect I didn't phrase those questions sufficiently clearly. Let me try again.
I understand that we are using a 5mil design rule clearance for the whole board. We have attempted to impose an additional requirement on the differential pairs for most of their length that the traces of the pair be 5mil from each other but at least 15mil from anything else (including other pairs). What I'm curious about is what copper violates this additional requirement that can't be moved, where is it, and how close does it actually come?
If we move the violating copper out to the 15mil boundary, that's great: problem solved. If we can't (or would really rather not), then let's consider where it is along the signal path, how close it is to the differential signals, and what net (signal) it is.
1. When in the signal path can we open up from 5mil to 15mil?
If that is part way down the first signal vias then we can try scaling the keepouts on our way through the board. From what I've seen, it looks like we have to get past sorting the signals out into pairs on layer 6 before we have room to do more than 5mil to foreign copper. Is that your understanding?
2. When do we need to scale back down to 5mil?
Is that at the signal vias for the two pairs that jump first to layer 1 for ESD? Or is it at the ESD lands?
What is the minimum frequency we will be running the HDMI at? (With version 1.4 the highest clock is 340MHz which implies 3.4GHz data rate on each data line. Thus I would expect good edges if we design for harmonics of 34GHz.;>)
:) 1920x1080p60. honestly though if it works at 1280x720p60 i'll be happy.
Again I wasn't clear enough with the question--I misled you by mentioning the highest clock frequency. To calculate the length characteristic for this taper, I need to figure out the lowest frequency (minimum) for which we want it to exhibit this impedance.
What is the vertical distance from layer to layer in our board stack?
it's a 6 layer 1.2mm PCB. if i have actually set the design parameters right (rather than just telling the factory manually) then the substrates are 1.35mil and the dielectrics 10mil
Good information. Thanks.
The idea is we can taper the keepouts on our signal vias near the A20 by the layer and avoid such an abrupt change from layer 1 to layer 6.
i would very much like to have used layer 3 instead of layer 6 for the HDMI signals long straightaway but it is too late now
It would then be stripline (uses 3 layers) instead of microstrip (2 layers). Stripline uses over and under reference planes.
Likewise, we can change the geometry of the keepout as we approach the ESD lands and finally the connector to likewise ease the transition.
okaaaay i think i understand what you mean.
[...]
There is one place in layer 6 where the space between the CLK pair and the adjacent data pair looks like it exceeds 35mil for a non-trivial distance. I think we could safely reintroduce a ground trace connecting the 2 or 3 vias in that space and thus keep the environment close to 15mil from differential trace to either ground or neighbouring signal.
good call. i know exactly where you mean. refresh URL and see new image.
Looks good. Thanks.
ok i did the taper at the DC3 connector end, and i think i got it reasonably ok at the A20 end. haven't run flood-fill. A20 end is a bit of a mess, bit unavoidable. left side is ok. right side... because of the immediate turn and the TX2 line...
The fine point of it is there is a particular curve involved in Klopfenstein and it requires a length which determines the frequency band over which you get the low reflection coefficient. That's why I'm trying to figure out what frequencies we care about and then see whether we can accommodate the length needed or we just have to make an approximation that is better than nothing.
so. i really want to wrap this up, and get the gerbers out.
loootta work... :)
Indeed. I am trying to reduce the feedback loop delay on this end.
Reference: [*] https://www.microwaves101.com/encyclopedias/klopfenstein-taper
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Wed, Sep 20, 2017 at 8:27 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
I'm interested to see what holes/voids and connections the power and ground planes have.
there are *no* connections on the GND planes. the power plane (and GND layers) interestingly have done a full surround on the HDMI vias. remember i had to separate them by an unusual distance.
What clearance to the fill do you have on the HDMI differential signal vias on layer 3, as opposed to 2, 4, and 5? I see it leaves a void on layer 3 but not on layer 4 (or presumably 2 or 5).
yehyeh. to be honest: i don't know exactly. or, i worked it out a long while ago, and can't remember precisely what it was.
What are the names of the power pins on the A20? What voltages do you supply it?
1.1, 1.25, 2.5 and 3.3v.
(Are any of them Vdiff+/-, e.g?)
no.
Good to know. Thanks.
I'm interested in tracking down the power supply pins for the differential HDMI signals as that is where our return path for common-mode signal has to go.
there's no specific power pin for HDMI. the GND pins are grouped in with a whole stack of other GND pins, there's absolutely no way it's practical to get a special GND plane to it: the board is extremely full already.
I'm not looking to provide any special connection to the power or ground pins. I just want to make sure we don't obstruct the return current path any more than necessary on its way from bottom reference ground plane (layer 5) to top reference ground plane (layer 2) to the power supply pins of the differential drivers:
- ground plane (layer 2) via to SoC ground pin land (layer 1)
- ground plane (layer 2) via to power supply decoupling capacitor
ground land (layer 1), through decoupling capacitor to land on power supply trace (layer 1), through trace to SoC power supply pin land (layer 1).
The goal is to avoid unnecessarily impeding this return current path. I'm trying to avoid making the path >~200mil and putting any major obstruction (like a huge layer void) in the way.
ok - i think i understand. the distance from the first set of vias to the nearest decoupling capacitors is 180mil. those are all at the centre of the A20 processor.
I've read a little (not nearly as much as I'd like, but I lack time) about using a taper to match impedance differences while minimizing the reflection coefficient.[*] I'm thinking we can use it at both ends of this layout to great advantage. We taper from 5mil clearance around the A20 on layer 1 to 15mil clearance on layer 6. Later we taper from 15mil clearance to whatever the closest copper is at the ESD and connector lands.
that's something that it would be helpful to have a rough diagram, even if it's hand-drawn [but see below: i think i understand it]
Once I figure out the frequency => characteristic taper length situation I'll try to send a drawing and/or image. In the meantime I've been looking at [*].
ooo wow fascinating.
hmmm... a bit too much to implement though. PADS can't really conveniently handle that kind of drawing (ok it can but it's a complete fricking pain. you're limited to 45 degree angles, and the mouse-drag is.. erratic in what it decides to allow you to move ).
Is the closest copper on layer 1, around the A20, 5mil from the HDMI differential signals?
yes. everything's 5 mil design rule.
What is the distance to the closest copper to the HDMI signals at the ESD lands?
5 mil
What is the distance to the closest copper to the HDMI signals at the connector lands?
5 mil
(I'm guessing in both cases it is likely the neighbouring lands. Is that correct?)
In retrospect I didn't phrase those questions sufficiently clearly. Let me try again.
sorry!
I understand that we are using a 5mil design rule clearance for the whole board.
except for the board edge, yes.
We have attempted to impose an additional requirement on the differential pairs for most of their length that the traces of the pair be 5mil from each other but at least 15mil from anything else (including other pairs). What I'm curious about is what copper violates this additional requirement that can't be moved, where is it, and how close does it actually come?
ah. ok. it's components. so, the EMI components, and the VIAs. and if the hand-drawn keepout isn't quite the right distance. ah. and IPSOUT (main power DC line) which i've just adjusted to be outside the 15mil boundary.
and... from the A20's pins: i put a GND trace round the back of the VIAs because the next row up includes all the USB signals. i didn't feel comfortable leaving that without a separation (again, 5mil clearance).
If we move the violating copper out to the 15mil boundary, that's great: problem solved. If we can't (or would really rather not), then let's consider where it is along the signal path, how close it is to the differential signals, and what net (signal) it is.
- When in the signal path can we open up from 5mil to 15mil?
If that is part way down the first signal vias then we can try scaling the keepouts on our way through the board. From what I've seen, it looks like we have to get past sorting the signals out into pairs on layer 6 before we have room to do more than 5mil to foreign copper. Is that your understanding?
no - that whole bottom area coming out from the A20 pins, on layer 1 is completely clear except for the GND vias which are staggered in between where they (immediately... 60 mil...) transition to layer 6.
on layer 6 they're clear of copper as well.
- When do we need to scale back down to 5mil?
Is that at the signal vias for the two pairs that jump first to layer 1 for ESD? Or is it at the ESD lands?
that sounds like a question you're asking yourself :)
What is the minimum frequency we will be running the HDMI at? (With version 1.4 the highest clock is 340MHz which implies 3.4GHz data rate on each data line. Thus I would expect good edges if we design for harmonics of 34GHz.;>)
:) 1920x1080p60. honestly though if it works at 1280x720p60 i'll be happy.
Again I wasn't clear enough with the question--I misled you by mentioning the highest clock frequency. To calculate the length characteristic for this taper, I need to figure out the lowest frequency (minimum) for which we want it to exhibit this impedance.
ah: i missed "minimum" rather than "maximum". ok 640x480@30hz is the lowest possible resolution that people would use...
The idea is we can taper the keepouts on our signal vias near the A20 by the layer and avoid such an abrupt change from layer 1 to layer 6.
i would very much like to have used layer 3 instead of layer 6 for the HDMI signals long straightaway but it is too late now
It would then be stripline (uses 3 layers) instead of microstrip (2 layers). Stripline uses over and under reference planes.
mmfh. ok understood.
ok i did the taper at the DC3 connector end, and i think i got it reasonably ok at the A20 end. haven't run flood-fill. A20 end is a bit of a mess, bit unavoidable. left side is ok. right side... because of the immediate turn and the TX2 line...
The fine point of it is there is a particular curve involved in Klopfenstein and it requires a length which determines the frequency band over which you get the low reflection coefficient.
yes. i saw the paper. that's going to be too complex to do. i'd have to construct it by hand in steps, of 45 degrees. or i can actually hand-edit the points and enter in numbers... but i have to create approximate points first (to get a valid non-intersecting polygon...)
honestly it's a bit too much hard work. if i was able to manipulate these things in e.g. python i'd say "let's go for it", immediately.
That's why I'm trying to figure out what frequencies we care about and then see whether we can accommodate the length needed or we just have to make an approximation that is better than nothing.
one step is fine - two or more gets _really_ awkward.
so. i really want to wrap this up, and get the gerbers out.
loootta work... :)
Indeed. I am trying to reduce the feedback loop delay on this end.
thx richard.
Reference: [*] https://www.microwaves101.com/encyclopedias/klopfenstein-taper
absolutely fascinating.
I had a bunch of rehearsals this afternoon, evening, and night. I'll write a technical response tomorrow morning when I'm not so tired.
On Thu, Sep 21, 2017 at 6:39 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
I had a bunch of rehearsals this afternoon, evening, and night. I'll write a technical response tomorrow morning when I'm not so tired.
good call.
l.
On Wed, Sep 20, 2017 at 4:22 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Wed, Sep 20, 2017 at 8:27 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
I'm interested to see what holes/voids and connections the power and ground planes have.
there are *no* connections on the GND planes. the power plane (and GND layers) interestingly have done a full surround on the HDMI vias. remember i had to separate them by an unusual distance.
What clearance to the fill do you have on the HDMI differential signal vias on layer 3, as opposed to 2, 4, and 5? I see it leaves a void on layer 3 but not on layer 4 (or presumably 2 or 5).
yehyeh. to be honest: i don't know exactly. or, i worked it out a long while ago, and can't remember precisely what it was.
Isn't it in the keepout of the HDMI differential signal vias on layer 3?
I'm not looking to provide any special connection to the power or ground pins. I just want to make sure we don't obstruct the return current path any more than necessary on its way from bottom reference ground plane (layer 5) to top reference ground plane (layer 2) to the power supply pins of the differential drivers:
- ground plane (layer 2) via to SoC ground pin land (layer 1)
- ground plane (layer 2) via to power supply decoupling capacitor
ground land (layer 1), through decoupling capacitor to land on power supply trace (layer 1), through trace to SoC power supply pin land (layer 1).
The goal is to avoid unnecessarily impeding this return current path. I'm trying to avoid making the path >~200mil and putting any major obstruction (like a huge layer void) in the way.
ok - i think i understand. the distance from the first set of vias to the nearest decoupling capacitors is 180mil. those are all at the centre of the A20 processor.
Sounds decent.
I've read a little (not nearly as much as I'd like, but I lack time) about using a taper to match impedance differences while minimizing the reflection coefficient.[*] I'm thinking we can use it at both ends of this layout to great advantage. We taper from 5mil clearance around the A20 on layer 1 to 15mil clearance on layer 6. Later we taper from 15mil clearance to whatever the closest copper is at the ESD and connector lands.
that's something that it would be helpful to have a rough diagram, even if it's hand-drawn [but see below: i think i understand it]
Once I figure out the frequency => characteristic taper length situation I'll try to send a drawing and/or image. In the meantime I've been looking at [*].
ooo wow fascinating.
hmmm... a bit too much to implement though. PADS can't really conveniently handle that kind of drawing (ok it can but it's a complete fricking pain. you're limited to 45 degree angles, and the mouse-drag is.. erratic in what it decides to allow you to move ).
I know, the curve is beautiful, but I think we can still improve the situation with straight lines. They had more space and thus changed the trace width to effect the change in impedance. We on the other hand have an unwanted change in impedance due to unavoidable constriction of clearance. Since the obstacles are immovable and cause an abrupt change in impedance, we have the option of tapering the clearance in order to soften the abruptness--and thus the reflection coefficient.
In other words, what you have done coincides with my idea of the best course of action.
Is the closest copper on layer 1, around the A20, 5mil from the HDMI differential signals?
yes. everything's 5 mil design rule.
I agree that 5mil is the design rule. The question is, "How close did we actually get?" What I'm referring to as foreign copper is any trace, via, component land/pad, or fill that is not part of the differential pair under consideration. In other words, did we make it from A20 land to via without getting closer than 10mil? 7mil? We can adjust the proximity of ground fill with a manual keepout if we need more space so I'm not too worried about that. I'm more curious about distance to other traces, lands/pads, or vias.
What is the distance to the closest copper to the HDMI signals at the ESD lands?
5 mil
Is that from the distance between ESD lands/pads or proximity of other traces or vias?
What is the distance to the closest copper to the HDMI signals at the connector lands?
5 mil
Again, is that from the distance between connector lands/pads or proximity of other traces or vias?
[...]
ah. ok. it's components. so, the EMI components, and the VIAs. and if the hand-drawn keepout isn't quite the right distance. ah. and IPSOUT (main power DC line) which i've just adjusted to be outside the 15mil boundary.
and... from the A20's pins: i put a GND trace round the back of the VIAs because the next row up includes all the USB signals. i didn't feel comfortable leaving that without a separation (again, 5mil clearance).
Both sound fine. We just want to establish at what point we can consider 15mil clearance a reasonable expectation and see whether we can make the transition smoother (less abrupt). And then, by the same token, at what point we are constrained to a smaller clearance so that we can again smooth the transition.
What is the minimum frequency we will be running the HDMI at? (With version 1.4 the highest clock is 340MHz which implies 3.4GHz data rate on each data line. Thus I would expect good edges if we design for harmonics of 34GHz.;>)
:) 1920x1080p60. honestly though if it works at 1280x720p60 i'll be happy.
Again I wasn't clear enough with the question--I misled you by mentioning the highest clock frequency. To calculate the length characteristic for this taper, I need to figure out the lowest frequency (minimum) for which we want it to exhibit this impedance.
ah: i missed "minimum" rather than "maximum". ok 640x480@30hz is the lowest possible resolution that people would use...
Is 1920x1080p60 is the maximum supported resolution under HDMI v1.4?
If so then 340MHz clock likely coincides with 1920x1080p60. =>340MHz * 640/1920 * 480/1080 * 30/60 = 340MHz * 1/3 * 4/9 * 1/2 ~= 25MHz
Well, that implies data rate of 250MHz and harmonics of 2.5GHz, and wavelength = velocity of propagation / frequency = 150um/ps / 2.5GHz = 6mm ~= 236mil
So if we can determine the closest encroachments then we can try to adjust the keepouts to ease between clearances.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Fri, Sep 22, 2017 at 8:51 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Wed, Sep 20, 2017 at 4:22 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Wed, Sep 20, 2017 at 8:27 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
I'm interested to see what holes/voids and connections the power and ground planes have.
there are *no* connections on the GND planes. the power plane (and GND layers) interestingly have done a full surround on the HDMI vias. remember i had to separate them by an unusual distance.
What clearance to the fill do you have on the HDMI differential signal vias on layer 3, as opposed to 2, 4, and 5? I see it leaves a void on layer 3 but not on layer 4 (or presumably 2 or 5).
yehyeh. to be honest: i don't know exactly. or, i worked it out a long while ago, and can't remember precisely what it was.
Isn't it in the keepout of the HDMI differential signal vias on layer 3?
i've not put in an HDMI keepout on layer 3 because there's no actual HDMI signals. there's some setting... somewhere... which makes a difference on GND copper pour / plane on layers 1, 3 and 6, where GND plane on 2 and 5 use a different clearance. i found it... *once*... about 2 years ago.
if it really really matters i can look around but it'll be a pain to find.
The goal is to avoid unnecessarily impeding this return current path. I'm trying to avoid making the path >~200mil and putting any major obstruction (like a huge layer void) in the way.
ok - i think i understand. the distance from the first set of vias to the nearest decoupling capacitors is 180mil. those are all at the centre of the A20 processor.
Sounds decent.
cool.
I've read a little (not nearly as much as I'd like, but I lack time) about using a taper to match impedance differences while minimizing the reflection coefficient.[*] I'm thinking we can use it at both ends of this layout to great advantage. We taper from 5mil clearance around the A20 on layer 1 to 15mil clearance on layer 6. Later we taper from 15mil clearance to whatever the closest copper is at the ESD and connector lands.
that's something that it would be helpful to have a rough diagram, even if it's hand-drawn [but see below: i think i understand it]
Once I figure out the frequency => characteristic taper length situation I'll try to send a drawing and/or image. In the meantime I've been looking at [*].
ooo wow fascinating.
hmmm... a bit too much to implement though. PADS can't really conveniently handle that kind of drawing (ok it can but it's a complete fricking pain. you're limited to 45 degree angles, and the mouse-drag is.. erratic in what it decides to allow you to move ).
I know, the curve is beautiful, but I think we can still improve the situation with straight lines. They had more space and thus changed the trace width to effect the change in impedance. We on the other hand have an unwanted change in impedance due to unavoidable constriction of clearance. Since the obstacles are immovable and cause an abrupt change in impedance, we have the option of tapering the clearance in order to soften the abruptness--and thus the reflection coefficient.
In other words, what you have done coincides with my idea of the best course of action.
oh! :)
Is the closest copper on layer 1, around the A20, 5mil from the HDMI differential signals?
yes. everything's 5 mil design rule.
I agree that 5mil is the design rule. The question is, "How close did we actually get?" What I'm referring to as foreign copper is any trace, via, component land/pad, or fill that is not part of the differential pair under consideration. In other words, did we make it from A20 land to via without getting closer than 10mil? 7mil? We can adjust the proximity of ground fill with a manual keepout if we need more space so I'm not too worried about that. I'm more curious about distance to other traces, lands/pads, or vias.
ok - let me re-run the flood fill and do a quick review, starting from the A20.
so. layer 1. surrounded, all 5mil. tracks are only 60mil or so to the VIAs. didn't do a keepout. all 5mil.
layer 3 (the VIAs) - some sort of curve on the flood-fill, it's 5mil but there's a void in the middle.
layer 6, starts @ 5mil, expands out to 15mil (mostly). exceptions: distance to TX2 "long wiggle" is 7mil, distance from bottom VIAs along board edge (to TXC), 11.2mil, distance to track *between* the VIAs 15mil. distance to GND vias ABOVE the hdmi tracks (TX2), 19mil.
in theory then i could move the entire set of horizontal tracks up by... 4 mil... i reeaallly don't want to though as it means redoing the whole f*****g lot of wiggles.... argh :)
at the other end all bets are off for distances after we get to the ESD pads.
What is the distance to the closest copper to the HDMI signals at the ESD lands?
5 mil
Is that from the distance between ESD lands/pads or proximity of other traces or vias?
there are no other traces other than GND. there are no other VIAs other than GND. the pad-to-pad clearance is about... 7mil. actually because of the keepout the flood-fill stays away... sooOo... some of the VIAs are 5mil, the rest are maybe... 7mil.
What is the distance to the closest copper to the HDMI signals at the connector lands?
5 mil
Again, is that from the distance between connector lands/pads or proximity of other traces or vias?
ok it's the taper i put into the keepout. there are no other traces, there is only GND vias. the taper in the keepout is the only point where the GND flood-fill gets to within 5mil.
i'll redo some pictures.
[...]
ah. ok. it's components. so, the EMI components, and the VIAs. and if the hand-drawn keepout isn't quite the right distance. ah. and IPSOUT (main power DC line) which i've just adjusted to be outside the 15mil boundary.
and... from the A20's pins: i put a GND trace round the back of the VIAs because the next row up includes all the USB signals. i didn't feel comfortable leaving that without a separation (again, 5mil clearance).
Both sound fine. We just want to establish at what point we can consider 15mil clearance a reasonable expectation and see whether we can make the transition smoother (less abrupt). And then, by the same token, at what point we are constrained to a smaller clearance so that we can again smooth the transition.
yehhh there are so many GND vias at the ESD end i'd question its effectiveness... the VIAs can't be moved, it's the only way they can get in on the DC3 connector.
What is the minimum frequency we will be running the HDMI at? (With version 1.4 the highest clock is 340MHz which implies 3.4GHz data rate on each data line. Thus I would expect good edges if we design for harmonics of 34GHz.;>)
:) 1920x1080p60. honestly though if it works at 1280x720p60 i'll be happy.
Again I wasn't clear enough with the question--I misled you by mentioning the highest clock frequency. To calculate the length characteristic for this taper, I need to figure out the lowest frequency (minimum) for which we want it to exhibit this impedance.
ah: i missed "minimum" rather than "maximum". ok 640x480@30hz is the lowest possible resolution that people would use...
Is 1920x1080p60 is the maximum supported resolution under HDMI v1.4?
yehyeh.
If so then 340MHz clock likely coincides with 1920x1080p60. =>340MHz * 640/1920 * 480/1080 * 30/60 = 340MHz * 1/3 * 4/9 * 1/2 ~= 25MHz
yehyeh.
Well, that implies data rate of 250MHz and harmonics of 2.5GHz, and wavelength = velocity of propagation / frequency = 150um/ps / 2.5GHz = 6mm ~= 236mil
So if we can determine the closest encroachments then we can try to adjust the keepouts to ease between clearances.
cool.
On Sep 22, 2017, at 04:17, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Fri, Sep 22, 2017 at 8:51 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Wed, Sep 20, 2017 at 4:22 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Wed, Sep 20, 2017 at 8:27 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
[…]
i've not put in an HDMI keepout on layer 3 because there's no actual HDMI signals. there's some setting... somewhere... which makes a difference on GND copper pour / plane on layers 1, 3 and 6, where GND plane on 2 and 5 use a different clearance. i found it... *once*... about 2 years ago.
if it really really matters i can look around but it'll be a pain to find.
After spending a couple minutes studying layers 3 and 4, here's what I see: 1. It looks like there may be a difference in the signal via antipads on layers 3 and 4 and that would be a way for us to give just that handful of vias special properties--if need be--although in this case it interestingly looks like the antipads are larger on layer 4 than layer 3. (optical illusion?) 2. The (minimum?) polygon size or line width of the fill looks larger on layer 3 than layer 4.
I think the second point, or something along those lines, likely explains the void on layer 3 and lack of void on layer 4. It looks like if we were to find and adjust that fill parameter on layer 3, some of your explicit guard traces might become redundant. (I can see why you added them because the ground fill wasn't working as expected.)
It would be nice to change layer 3 to make the signal path more uniform on the way through the vias but it's not the end of the world if we can't, as long as layers 2 and 5 resemble layer 4 in the vicinity of the HDMI differential signal vias adjacent to the A20.
I know, the curve is beautiful, but I think we can still improve the situation with straight lines. They had more space and thus changed the trace width to effect the change in impedance. We on the other hand have an unwanted change in impedance due to unavoidable constriction of clearance. Since the obstacles are immovable and cause an abrupt change in impedance, we have the option of tapering the clearance in order to soften the abruptness--and thus the reflection coefficient.
In other words, what you have done coincides with my idea of the best course of action.
oh! :)
The remaining questions are where do we impose 5mil clearance (by bringing in the fill), where do we start tapering, and what does the taper look like? Likewise, but in reverse order, at the other end.
Is the closest copper on layer 1, around the A20, 5mil from the HDMI differential signals?
yes. everything's 5 mil design rule.
I agree that 5mil is the design rule. The question is, "How close did we actually get?" What I'm referring to as foreign copper is any trace, via, component land/pad, or fill that is not part of the differential pair under consideration. In other words, did we make it from A20 land to via without getting closer than 10mil? 7mil? We can adjust the proximity of ground fill with a manual keepout if we need more space so I'm not too worried about that. I'm more curious about distance to other traces, lands/pads, or vias.
ok - let me re-run the flood fill and do a quick review, starting from the A20.
so. layer 1. surrounded, all 5mil. tracks are only 60mil or so to the VIAs. didn't do a keepout. all 5mil.
layer 3 (the VIAs) - some sort of curve on the flood-fill, it's 5mil but there's a void in the middle.
Are layers 2, 4, and 5 also 5mil away from the differential signal at the vias?
layer 6, starts @ 5mil, expands out to 15mil (mostly). exceptions: distance to TX2 "long wiggle" is 7mil, distance from bottom VIAs along board edge (to TXC), 11.2mil, distance to track *between* the VIAs 15mil. distance to GND vias ABOVE the hdmi tracks (TX2), 19mil.
in theory then i could move the entire set of horizontal tracks up by... 4 mil... i reeaallly don't want to though as it means redoing the whole f*****g lot of wiggles.... argh :)
Can't select and move? That does stink! Evening out the clearance does help lower the difference in impedance seen by the traces in the TXC pair (one had 15mil to foreign signal, the other 11.2mil) and the TX2 pair (one had 15mil to foreign signal, the other 19mil). Impedance imbalance between the traces of a differential pair moves energy from differential mode to single-ended mode (between trace and reference) which will try harder to radiate (EMI).
Since it is such a long section it would be beneficial to move the traces. If we were to redraw the wiggles I would suggest we take care to separate parallel sections of the same trace by at least 4 times the trace width (4*5mil=20mil)--especially for TX2.[Toradex, p. 17] This is because at these frequencies, if the same trace is too close and parallel, the signal will hop straight across.
So if we bring in the keepout at 5mil on layer 6 and taper it slowly to 7mil by the point we get to the TX2 wiggle which exhibits 7mil clearance. To make this work we have to start the pairs off around 5mil inter-pair spacing and then spread them as we taper the keepout. I realize this is more complicated than what I first described.
at the other end all bets are off for distances after we get to the ESD pads.
What is the distance to the closest copper to the HDMI signals at the ESD lands?
5 mil
Is that from the distance between ESD lands/pads or proximity of other traces or vias?
there are no other traces other than GND. there are no other VIAs other than GND. the pad-to-pad clearance is about... 7mil. actually because of the keepout the flood-fill stays away... sooOo... some of the VIAs are 5mil, the rest are maybe... 7mil.
What is the distance to the closest copper to the HDMI signals at the connector lands?
5 mil
Again, is that from the distance between connector lands/pads or proximity of other traces or vias?
ok it's the taper i put into the keepout. there are no other traces, there is only GND vias. the taper in the keepout is the only point where the GND flood-fill gets to within 5mil.
i'll redo some pictures.
[...]
ah. ok. it's components. so, the EMI components, and the VIAs. and if the hand-drawn keepout isn't quite the right distance. ah. and IPSOUT (main power DC line) which i've just adjusted to be outside the 15mil boundary.
and... from the A20's pins: i put a GND trace round the back of the VIAs because the next row up includes all the USB signals. i didn't feel comfortable leaving that without a separation (again, 5mil clearance).
Both sound fine. We just want to establish at what point we can consider 15mil clearance a reasonable expectation and see whether we can make the transition smoother (less abrupt). And then, by the same token, at what point we are constrained to a smaller clearance so that we can again smooth the transition.
yehhh there are so many GND vias at the ESD end i'd question its effectiveness...
You'd question the effectiveness of what? The ESD component? The taper?
the VIAs can't be moved, it's the only way they can get in on the DC3 connector.
What is the minimum frequency we will be running the HDMI at? (With version 1.4 the highest clock is 340MHz which implies 3.4GHz data rate on each data line. Thus I would expect good edges if we design for harmonics of 34GHz.;>)
:) 1920x1080p60. honestly though if it works at 1280x720p60 i'll be happy.
Again I wasn't clear enough with the question--I misled you by mentioning the highest clock frequency. To calculate the length characteristic for this taper, I need to figure out the lowest frequency (minimum) for which we want it to exhibit this impedance.
ah: i missed "minimum" rather than "maximum". ok 640x480@30hz is the lowest possible resolution that people would use...
Is 1920x1080p60 is the maximum supported resolution under HDMI v1.4?
yehyeh.
If so then 340MHz clock likely coincides with 1920x1080p60. =>340MHz * 640/1920 * 480/1080 * 30/60 = 340MHz * 1/3 * 4/9 * 1/2 ~= 25MHz
yehyeh.
Well, that implies data rate of 250MHz and harmonics of 2.5GHz, and wavelength = velocity of propagation / frequency = 150um/ps / 2.5GHz = 6mm ~= 236mil
So if we can determine the closest encroachments then we can try to adjust the keepouts to ease between clearances.
cool.
On Sat, Sep 23, 2017 at 8:26 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
After spending a couple minutes studying layers 3 and 4, here's what I see:
- It looks like there may be a difference in the signal via antipads on layers 3 and 4 and that would be a way for us to give just that handful of vias special properties--if need be--although in this case it interestingly looks like the antipads are larger on layer 4 than layer 3. (optical illusion?)
- The (minimum?) polygon size or line width of the fill looks larger on layer 3 than layer 4.
layer 4 HDMI vias are actually covered by VCC 3v3 flood-filled plane. it's a 5mil clearance to that. i decided i didn't like that, so i made a cut-back in the 3V3 plane so that GND covers it instead. it's *still* 5mil even on that flood fill.
so it's just something weird about the flood-fill on layer 3, possibly due to it being a copper pour not a "plane area". don't know. if absolutely necessary i can put in some tracks that split the pairs.
I think the second point, or something along those lines, likely explains the void on layer 3 and lack of void on layer 4. It looks like if we were to find and adjust that fill parameter on layer 3, some of your explicit guard traces might become redundant. (I can see why you added them because the ground fill wasn't working as expected.)
It would be nice to change layer 3 to make the signal path more uniform on the way through the vias but it's not the end of the world if we can't, as long as layers 2 and 5 resemble layer 4 in the vicinity of the HDMI differential signal vias adjacent to the A20.
i have to use it as a signal layer, so there's tracks running round the back of some of the diff-pair VIAs.
The remaining questions are where do we impose 5mil clearance (by bringing in the fill), where do we start tapering, and what does the taper look like? Likewise, but in reverse order, at the other end.
yehyeh
> Is the closest copper on layer 1, around the A20, 5mil from the HDMI > differential signals?
yes. everything's 5 mil design rule.
I agree that 5mil is the design rule. The question is, "How close did we actually get?" What I'm referring to as foreign copper is any trace, via, component land/pad, or fill that is not part of the differential pair under consideration. In other words, did we make it from A20 land to via without getting closer than 10mil? 7mil? We can adjust the proximity of ground fill with a manual keepout if we need more space so I'm not too worried about that. I'm more curious about distance to other traces, lands/pads, or vias.
ok - let me re-run the flood fill and do a quick review, starting from the A20.
so. layer 1. surrounded, all 5mil. tracks are only 60mil or so to the VIAs. didn't do a keepout. all 5mil.
layer 3 (the VIAs) - some sort of curve on the flood-fill, it's 5mil but there's a void in the middle.
Are layers 2, 4, and 5 also 5mil away from the differential signal at the vias?
yes. layer 3 is the only exception.
layer 6, starts @ 5mil, expands out to 15mil (mostly). exceptions: distance to TX2 "long wiggle" is 7mil, distance from bottom VIAs along board edge (to TXC), 11.2mil, distance to track *between* the VIAs 15mil. distance to GND vias ABOVE the hdmi tracks (TX2), 19mil.
in theory then i could move the entire set of horizontal tracks up by... 4 mil... i reeaallly don't want to though as it means redoing the whole f*****g lot of wiggles.... argh :)
Can't select and move?
you can... but there are special rules which ensure that 45 degree angles on two adjacent segments are "respected". it gets extremely weird and extremely frustrating.
Since it is such a long section it would be beneficial to move the traces.
argh. i kinda reached that conclusion :)
what i can do to some degree is manually enter values (adding 4mil up and 4 mil left/right) so that there's less to redo by hand.
So if we bring in the keepout at 5mil on layer 6 and taper it slowly to 7mil by the point we get to the TX2 wiggle which exhibits 7mil clearance. To make this work we have to start the pairs off around 5mil inter-pair spacing and then spread them as we taper the keepout. I realize this is more complicated than what I first described.
it's too much. i can just about manage adding 4mil manually to every single one of those long straights, moving them up from the 11mil clearance to the bottom board-line VIAs to 15mil, thus taking 4mil off that 19mil clearance and resulting in 15mil there as well.
we don't have *room* for 7 mil inter-pair spacing.
if i've misunderstood, do let me know.
yehhh there are so many GND vias at the ESD end i'd question its effectiveness...
You'd question the effectiveness of what? The ESD component? The taper?
putting in a taper at the end is significantly disrupted by the presence of non-removable VIAs. you can *add* a taper... but then the VIAs (which cannot be moved) are *already* within about 5mil or 7mil of the tracks.
what *would* work is bringing the taper in *BEFORE* the ESD components. it also coincides with the double 45-degree bending of the group of tracks, so is still a bit... dodgy.
see this picture for reference: http://rhombus-tech.net/allwinner_a10/news/eoma68-a20-275-layer6-hdmi.jpg
basically there's no point in tapering *after* the ESD components because the GND vias are already closer than the taper would bring GND in.
l.
http://rhombus-tech.net/allwinner_a10/news/eoma68-a20-hdmi-275-new-keepout-t...
hiya richard ok this is what i meant about doing the taper prior to the ESD protection because the VIAs are *already* close and can't be moved.
i just realised i missed out HXT1 so i'll alter that... done...
thoughts?
l.
On Sep 23, 2017, at 03:47, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Sat, Sep 23, 2017 at 8:26 AM, Richard Wilbur richard.wilbur@gmail.com wrote: […] so it's just something weird about the flood-fill on layer 3, possibly due to it being a copper pour not a "plane area". don't know. if absolutely necessary i can put in some tracks that split the pairs.
I guess we don't have to worry about layer 3 if it's going to be that uncooperative and we don't gain that much by making the desired changes.
It would be nice to change layer 3 to make the signal path more uniform on the way through the vias but it's not the end of the world if we can't, as long as layers 2 and 5 resemble layer 4 in the vicinity of the HDMI differential signal vias adjacent to the A20.
i have to use it as a signal layer, so there's tracks running round the back of some of the diff-pair VIAs.
Not a big deal.
The remaining questions are where do we impose 5mil clearance (by bringing in the fill), where do we start tapering, and what does the taper look like? Likewise, but in reverse order, at the other end.
yehyeh
If we choose to have copper fill at both ends with 5mil clearance--which will go a long way towards keeping the fields symmetric where we are trying to sort things out and don't have the space to consistently maintain a larger clearance--then in order to keep the fields symmetric as we taper up to larger clearance we need to first bring the differential pairs alongside each other at 5mil inter-pair spacing (between pairs or pair-to-pair). This is so we have better control of spacing because the smallest copper we can insert is 5mil but the smallest space is much smaller.
Then to taper up, we have two options: 1. spread in both directions from the inner 2 pairs, or 2. spread to one side or the other. If we spread from the middle then the inner two pairs end up shorter than the outer two whereas if we spread from one side the straight pairs will be shorter then those which tapered away. I'm going to suggest that when we spread we move to the left which would lengthen the CLK lines more than any other.
Also, the taper at the ESD end should fold in from the bottom (CLK side). At that end maybe we come from 15mil to 7mil before the ESD lands, if that's the best consistent clearance through the ESD lands, then taper to 5mil before the constraining copper and maintain 5mil to the connector.
so. layer 1. surrounded, all 5mil. tracks are only 60mil or so to the VIAs. didn't do a keepout. all 5mil.
layer 3 (the VIAs) - some sort of curve on the flood-fill, it's 5mil but there's a void in the middle.
Are layers 2, 4, and 5 also 5mil away from the differential signal at the vias?
yes. layer 3 is the only exception.
Good. Then for the HDMI high-frequency effort we can pretty much ignore it--especially if we can't fix the source of non-uniformity/asymmetry.
layer 6, starts @ 5mil, expands out to 15mil (mostly). exceptions: distance to TX2 "long wiggle" is 7mil, distance from bottom VIAs along board edge (to TXC), 11.2mil, distance to track *between* the VIAs 15mil. distance to GND vias ABOVE the hdmi tracks (TX2), 19mil.
in theory then i could move the entire set of horizontal tracks up by... 4 mil... i reeaallly don't want to though as it means redoing the whole f*****g lot of wiggles.... argh :)
Can't select and move?
you can... but there are special rules which ensure that 45 degree angles on two adjacent segments are "respected". it gets extremely weird and extremely frustrating.
Since it is such a long section it would be beneficial to move the traces.
argh. i kinda reached that conclusion :)
what i can do to some degree is manually enter values (adding 4mil up and 4 mil left/right) so that there's less to redo by hand.
So if we bring in the keepout at 5mil on layer 6 and taper it slowly to 7mil by the point we get to the TX2 wiggle which exhibits 7mil clearance. To make this work we have to start the pairs off around 5mil inter-pair spacing and then spread them as we taper the keepout. I realize this is more complicated than what I first described.
it's too much. i can just about manage adding 4mil manually to every single one of those long straights, moving them up from the 11mil clearance to the bottom board-line VIAs to 15mil, thus taking 4mil off that 19mil clearance and resulting in 15mil there as well.
we don't have *room* for 7 mil inter-pair spacing.
if i've misunderstood, do let me know.
I'm pretty sure you have misunderstood: We presently have 15mil inter-pair spacing (distance between adjacent pairs) over most of the length and 5mil intra-pair spacing (distance between traces within a pair).
yehhh there are so many GND vias at the ESD end i'd question its effectiveness...
You'd question the effectiveness of what? The ESD component? The taper?
putting in a taper at the end is significantly disrupted by the presence of non-removable VIAs. you can *add* a taper... but then the VIAs (which cannot be moved) are *already* within about 5mil or 7mil of the tracks.
what *would* work is bringing the taper in *BEFORE* the ESD components. it also coincides with the double 45-degree bending of the group of tracks, so is still a bit... dodgy.
see this picture for reference: http://rhombus-tech.net/allwinner_a10/news/eoma68-a20-275-layer6-hdmi.jpg
basically there's no point in tapering *after* the ESD components because the GND vias are already closer than the taper would bring GND in.
I agree. I was going to suggest tapering down the keepout along with the inter-pair spacing before we get to the ESD lands. Maybe even before we get to the vias.
I realize this could interfere with the intra-pair skew compensation at the corners if we don't work out the logistics carefully.
If we have to choose an end to work on, I'd pick the connector end as it's further from the signal source and thus more likely to cause signal integrity issues.
On Tue, Sep 26, 2017 at 7:00 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Sep 23, 2017, at 03:47, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Sat, Sep 23, 2017 at 8:26 AM, Richard Wilbur richard.wilbur@gmail.com wrote: […] so it's just something weird about the flood-fill on layer 3, possibly due to it being a copper pour not a "plane area". don't know. if absolutely necessary i can put in some tracks that split the pairs.
I guess we don't have to worry about layer 3 if it's going to be that uncooperative and we don't gain that much by making the desired changes.
wheww :)
Then to taper up, we have two options:
- spread in both directions from the inner 2 pairs,
or 2. spread to one side or the other.
If we spread from the middle then the inner two pairs end up shorter than the outer two whereas if we spread from one side the straight pairs will be shorter then those which tapered away. I'm going to suggest that when we spread we move to the left which would lengthen the CLK lines more than any other.
ok the two diagrams are great, they explain clearly what you're suggesting. and still after misunderstanding it i think i finally get it... that you need to do the tapers simultaneously on *all* pairs... and i don't believe it's possible.
... bear in mind i really don't want to modify these tracks... :) i took out those GND spacings i was using to maintain separation...
basically, it's down to the GND vias in between which are right where we want to do the tapering. up until you get past the GND vias - which are there to protect the diff-pair VIAs - all clearances are 5mil. it's the only way to have gotten the 5mil tracks in between the A20 BGA pads, for example, it's the only way to squeeze between the GND vias and still maintain straight (vertical) tracks of identical length and so on.
in order to have the taper just before, it would be necessary to *close* the pairs together to a 5mil intra-pair spacing *after* the VIAs... and *then* re-open them back up again! and that's right where we want to do the wiggles... which would then have to be delayed... which they can't be because there's not enough room to put them on the straightaway.... or if they weren't they delayed then the reduced space starts interfering with how the wiggles are created....
basically it's massively complicated, and is far more than i would like to attempt at this late stage.
Also, the taper at the ESD end should fold in from the bottom (CLK side). At that end maybe we come from 15mil to 7mil before the ESD lands, if that's the best consistent clearance through the ESD lands, then taper to 5mil before the constraining copper and maintain 5mil to the connector.
again: the GND vias prevent that from being possible, but in this case there is also the 45-degree length-correction wiggles to consider.
now, what *might* work is putting in a very thin triangular wedge coming off (and on) each GND via, but in doing so i remember there are problems with having sharp points.
in short i don't believe it's possible, and it's getting late in the day to try experimenting.
I agree. I was going to suggest tapering down the keepout along with the inter-pair spacing before we get to the ESD lands. Maybe even before we get to the vias.
there's been some cross-over, i've done an update to the images on the website since.
l.
On Sep 26, 2017, at 01:16, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Tue, Sep 26, 2017 at 7:00 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
Then to taper up, we have two options:
- spread in both directions from the inner 2 pairs,
or 2. spread to one side or the other.
If we spread from the middle then the inner two pairs end up shorter than the outer two whereas if we spread from one side the straight pairs will be shorter then those which tapered away. I'm going to suggest that when we spread we move to the left which would lengthen the CLK lines more than any other.
ok the two diagrams are great, they explain clearly what you're suggesting. and still after misunderstanding it i think i finally get it... that you need to do the tapers simultaneously on *all* pairs... and i don't believe it's possible.
I understand it may not be possible to do the taper in the space we have available. I just wanted to note the minimum length in the signal propagation direction for the two geometries of the taper of the inter-pair clearance between 5 and 15mil: 1. spread/contract from/towards the middle: 15mil 2. spread/contract from/towards one side: 30mil
... bear in mind i really don't want to modify these tracks... :) i took out those GND spacings i was using to maintain separation...
basically, it's down to the GND vias in between which are right where we want to do the tapering. up until you get past the GND vias - which are there to protect the diff-pair VIAs - all clearances are 5mil. it's the only way to have gotten the 5mil tracks in between the A20 BGA pads, for example, it's the only way to squeeze between the GND vias and still maintain straight (vertical) tracks of identical length and so on.
in order to have the taper just before, it would be necessary to *close* the pairs together to a 5mil intra-pair spacing *after* the VIAs... and *then* re-open them back up again! and that's right where we want to do the wiggles... which would then have to be delayed... which they can't be because there's not enough room to put them on the straightaway.... or if they weren't they delayed then the reduced space starts interfering with how the wiggles are created....
basically it's massively complicated, and is far more than i would like to attempt at this late stage.
We certainly don't have to do any specific explicit taper. We're getting one for free at the connector end with the ESD and connector lands.
I guess I'd be reticent to impose a taper that doesn't either maintain or improve the symmetry of clearances and impedances. I don't think we would necessarily call it progress if we reduced the reflection coefficient on a few traces and simultaneously increased the impedance imbalance between the traces of one or more differential pairs (shifting signal energy from differential to single-ended conduction, raising the spectre of EMI).
Also, the taper at the ESD end should fold in from the bottom (CLK side). At that end maybe we come from 15mil to 7mil before the ESD lands, if that's the best consistent clearance through the ESD lands, then taper to 5mil before the constraining copper and maintain 5mil to the connector.
again: the GND vias prevent that from being possible, but in this case there is also the 45-degree length-correction wiggles to consider.
Problematic, I agree.
now, what *might* work is putting in a very thin triangular wedge coming off (and on) each GND via, but in doing so i remember there are problems with having sharp points.
in short i don't believe it's possible, and it's getting late in the day to try experimenting.
That it is.
By the way, I was reading Toradex, page 23 to review their recommendations regarding intra-pair skew compensation (the wiggles) and happened to notice that they actually said that turns within 15mm(millimeters not mils!!!) are close enough that, if complementary, can be considered to have cancelled out the intra-pair skew so that no compensation is needed. 15mm ~= 590mil! Oops, I misquoted that value as 15mil in my earlier recommendations! Sorry about the mistake, that value is actually a good deal more forgiving and generous than I made it sound.
That could even obviate the need for all of our intra-pair skew compensation on the connector side of the long horizontal straight section! How far are the turns from each other? Just eyeballing it I'd say consecutive turns are no more than 150mil from each other on the ascending section (heading northeast).
I agree. I was going to suggest tapering down the keepout along with the inter-pair spacing before we get to the ESD lands. Maybe even before we get to the vias.
there's been some cross-over, i've done an update to the images on the website since.
Let's go with the layer 6 that doesn't have an explicit taper.[*] It's more symmetric for all the pairs and open like layer 1 at the connector end.
I thank you for all the hard work you've put in on this effort--laying things out, re-laying things out, adjusting things, and pushing back on things that sound bad or don't make sense till either I see they don't make sense or you see that they do.
Reference:
[*] http://rhombus-tech.net/allwinner_a10/news/eoma68-a20-275-layer6-hdmi.jpg
http://rhombus-tech.net/allwinner_a10/news/eoma68-a20-hdmi-275-new-keepout-t...
ok that's the latest, a few tweaks still needed. yes saw about the 15mm not 15mil... whoops :) so all those little tweaks... gone. maybe shouldn't have removed the ones on the USB-OTG line but... oh well.
anyway... moved the tracks up by 4 mil so they're now 15 mil from board-edge GND and 15 mil from the top line. sorted out the wiggles (aagain!!).
taper... really not certain where to put it (starting point) - thoughts appreciated.
end... just before the 45-degree bend into the VIAs and ESD.
a few tweaks of VIAs along the way to ensure the GND flood-fill isn't broken. the image is hi-res enough so that GND VIAs (covered by flood-fill) can just be identified by the word "GND".
l.
On Sep 28, 2017, at 03:36, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
http://rhombus-tech.net/allwinner_a10/news/eoma68-a20-hdmi-275-new-keepout-t...
ok that's the latest, a few tweaks still needed. yes saw about the 15mm not 15mil... whoops :) so all those little tweaks... gone. maybe shouldn't have removed the ones on the USB-OTG line but... oh well.
HDMI looks good without the little wiggles (which, it turns out, weren't essential) towards the connector side. I didn't notice the wiggles on the USB OTG lines. Were they in the pictures you released?
anyway... moved the tracks up by 4 mil so they're now 15 mil from board-edge GND and 15 mil from the top line.
Very nice! It looks cleaner and more symmetric.
sorted out the wiggles (again!!).
Courage, mate. Be careful in the wiggles if you make a high-frequency trace turn parallel to itself that those parallel sections are at least separated by a distance of 4*trace width=20mil. Otherwise the parallel sections look like antennae to the high-frequency signals which simply radiate straight across and bypass the intended delay path.
I notice some of your wiggles have no parallel sections and some do.
taper... really not certain where to put it (starting point) - thoughts appreciated.
What type of taper? An approximation of Klopfenstein, or just a symmetric easing of the transition?
end... just before the 45-degree bend into the VIAs and ESD.
That's a fine place to end it.
Along the bottom margin there's a little corner in the fill that sticks out towards the trace where the keepout geometry crosses the 5mil clearance. Not to worry, it will disappear with my recommendations for the taper.
Can I send a diagram this evening?
a few tweaks of VIAs along the way to ensure the GND flood-fill isn't broken. the image is hi-res enough so that GND VIAs (covered by flood-fill) can just be identified by the word "GND".
Thanks. Looks good.
hiya richard, getting there, thx for this - will reply tomorrow. yes of course, send diagram. l.
Be careful in the wiggles if you make a high-frequency trace turn parallel to itself that those parallel sections are at least separated by a distance of 4*trace width=20mil. Otherwise the parallel sections look like antennae to the high-frequency signals which simply radiate straight across and bypass the intended delay path.
In other words if the edge of the copper of a trace faces a different part of the same trace, the electric field will overlap significantly if they aren't far enough apart and the signal will jump the gap.
I painted the likely problematic edges with red and circled in green the wiggle you created with a geometry that completely avoids the problem.
For recommended wiggle dimensions consult Toradex, p. 22, figure 23, (reproduced below for convenience of discussion):
Here s = spacing between traces of a differential pair = 5mil (for our layout) w = width of traces in differential pair = 5mil (for our layout)
Hence, Toradex suggests deviating away no more than 10mil and staying at that distance no more than 15mil. I would suggest spending less distance away, say 7.5mil before turning back so that we get more length at a 45 degree angle with the other trace which is where we make up path length.
Regarding the taper, I am sure we don't want to reduce the spacing over a long enough distance to reduce the impedance below the HDMI tolerance: differential = 100 +/-15% Ohm = [85,115] Ohm, single-ended = 55 +/15% Ohm = [42.5,57.5] Ohm.
What does PADS report for the impedance of our HDMI differential traces on the current or a recent layout?
(We opened up the clearance to 15mil around the differential pairs in order to try to keep the impedance up.) If the impedance is too low, we may need to forgo the taper altogether and just live with the small discontinuities caused by a few vias and component lands that are significantly closer.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Mon, Oct 2, 2017 at 5:01 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
Be careful in the wiggles if you make a high-frequency trace turn parallel to itself that those parallel sections are at least separated by a distance of 4*trace width=20mil.
yyehhh it's a bitch doing these by hand.
I painted the likely problematic edges with red and circled in green the wiggle you created with a geometry that completely avoids the problem.
yehyeh thank you for that, makes it really clear. the thing is there's really not a lot of space, in which we need to get rid of about... i think it's something like almost 0.8mm length discrepancy: difference between two BGA pads *and* the right-angle turn. the toradex-recommended wiggle method is fine for compensating for a single 45 degree turn (found that out a few weeks back, now) but for the amount of length discrepancy here it would be something like... maybe... eight or nine toradex-style wiggles.
i'll see how it looks.
l.
ok so... blegh. as i suspected, using the toradex recommended wiggle layout results in the extension of the use of wiggles for well over 150 possible 200 mils. 0.2 inches! that's over 5mm!
the use of only a 45 degree bend basically results only in 2 * (2-sqrt(2)) * 7 or so being added to the length. when you use a U-shaped wiggle that becomes 2 * (2-sqrt(2) * 7 _and_ 2 * (sqrt(2) * 7 _and_ whatever length is on the uprights of the U.
getting fed up of doing these by hand. i'll use the accordion feature. it makes them curved but at least it will be a regular / fixed distance... i wonder if i can switch off the curves... yes you can! ok i'll give that a shot.
l.
The alternative is to use the "U"-shaped with spacing of at least 20mil between facing copper of the same trace.
I agree you are better off when trying to add length to use the 45° corners rather than the arcs since arcs are known for turning a corner with minimal distance.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Mon, Oct 2, 2017 at 10:15 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
The alternative is to use the "U"-shaped with spacing of at least 20mil between facing copper of the same trace.
yyeah that's 4x track width... it's gonna be really really tight to get 20 mil in. will see.
I agree you are better off when trying to add length to use the 45° corners rather than the arcs since arcs are known for turning a corner with minimal distance.
... they are? :)
On Mon, Oct 2, 2017 at 10:33 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Mon, Oct 2, 2017 at 10:15 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
The alternative is to use the "U"-shaped with spacing of at least 20mil between facing copper of the same trace.
yyeah that's 4x track width... it's gonna be really really tight to get 20 mil in. will see.
it was. best i could do (attached) - accordion wasn't having any of it, had to do them by hand.
the defaults in PADS for the gap separation btw were set to 2x. 4x seems an _awful_ lot, to my eye: i don't believe i've ever seen wiggles with such large separation. are you sure the app note didn't mean "4x separation centre-to-centre of the traces"? or, was the app note specifically applying to really *really* high frequency traces (above say... 2 or even 3 ghz)?
l.
On Oct 2, 2017, at 19:56, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Mon, Oct 2, 2017 at 10:33 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Mon, Oct 2, 2017 at 10:15 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
The alternative is to use the "U"-shaped with spacing of at least 20mil between facing copper of the same trace.
yyeah that's 4x track width... it's gonna be really really tight to get 20 mil in. will see.
it was. best i could do (attached) - accordion wasn't having any of it, had to do them by hand.
the defaults in PADS for the gap separation btw were set to 2x. 4x seems an _awful_ lot, to my eye: i don't believe i've ever seen wiggles with such large separation. are you sure the app note didn't mean "4x separation centre-to-centre of the traces"? or, was the app note specifically applying to really *really* high frequency traces (above say... 2 or even 3 ghz)?
Toradex, p. 17, section 6.2 as illustrated in figure 13.
It matters more the greater the length of facing copper. So if you can only get 15mil separation but split it into two or more wiggles, that would be better than having one wiggle at 15mil separation (between facing copper of the same trace).
On Tue, Oct 3, 2017 at 8:48 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
the defaults in PADS for the gap separation btw were set to 2x. 4x seems an _awful_ lot, to my eye: i don't believe i've ever seen wiggles with such large separation. are you sure the app note didn't mean "4x separation centre-to-centre of the traces"? or, was the app note specifically applying to really *really* high frequency traces (above say... 2 or even 3 ghz)?
Toradex, p. 17, section 6.2 as illustrated in figure 13.
It matters more the greater the length of facing copper. So if you can only get 15mil separation but split it into two or more wiggles, that would be better than having one wiggle at 15mil separation (between facing copper of the same trace).
ok understood. sorry took a while to reply.
ok so i think what i'll do is, turn HX1T into two wiggles (still with 20mil separation), there's space to do that, but otherwise leave everything else alone.
nearly there - i still have to reply to the message a few days ago about the keepout area.
l.
You probably already mentioned it but what is the spacing between the copper of the A20 pads/lands?
On Oct 6, 2017, at 12:19, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
sorry took a while to reply.
No worries. I took a careful look at my E-mail messages to make sure I hadn't missed something from you. (I was concerned that maybe the ball was actually in my court without me being aware of the fact.)
ok so i think what i'll do is, turn HX1T into two wiggles (still with 20mil separation), there's space to do that, but otherwise leave everything else alone.
Sounds good.
nearly there - i still have to reply to the message a few days ago about the keepout area.
I'll try to elaborate further when I get home and in striking distance of a more powerful paint program.
Richard
On Fri, Oct 6, 2017 at 10:45 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
nearly there - i still have to reply to the message a few days ago about the keepout area.
I'll try to elaborate further when I get home and in striking distance of a more powerful paint program.
mythbusters. definitely mythbusters. you want C-4, a 1 ton deathstar (jamie's creation), and a "house at the alameda county bomb range".
https://www.discovery.com/tv-shows/mythbusters/videos/explosive-painting-aft...
... back to our reguarly-scheduled programme...
http://rhombus-tech.net/allwinner_a10/news/eoma68-a20-275-hdmi-new-wiggles-l...
so a different program (PADS Router) this time, sorry i had one of the tracks highlighted when i ran import -window root... i moved TX2's wiggle to the right a bit, that gave me some space to get 2 20-ish mil wiggles on TX1 instead of one reaally large one. not enough space to do the same thing for TX0 or TX2.
reason for showing you the router view is, keepouts are clearly hatched (it's a bit of a pain to work with to be honest, don't know how to switch it off..) but the extent of the keepout area is much clearer. anything outside of that will be 5mil clearance, i used that fact at the right end to just... let flood-fill go round all the VIAs, tracks and ESD components @ 5mil.
two grey dots (one overlapping one of the hdmi tracks) which don't have white in them are component-centres and can be ignored.
l.
Your change to TX1 definitely looks like an improvement.
In order to make a determination on the best course of action regarding the keepout at the connector end and whether to recommend some type of taper I still have a burning question:
What does PADS currently give as the impedance of the HDMI differential lines? Does it give an impedance for a particular trace? (That would likely be the single-ended impedance.) Does it offer a differential impedance value for a pair of traces?
If PADS offers us some impedance values, then we can compare those with the specification to determine whether we are within the specified tolerances and, if so, whether we have enough room to spend more impedance on a taper.
If we are outside the specified impedance tolerance, then we need to take measures to get back within tolerance.
If we are barely inside the tolerance, we can probably only make some slight adjustments to try to move the impedance closer to nominal and/or minimize reflections.
If we are well within the specified tolerance, we can consider some taper of clearances and keepouts to minimize reflections.
Afterthought: If PADS does give impedance values, please include the values for each of the HDMI differential traces and a URL to images of the top and bottom layers of that layout.
That way I'll be able to make recommendations and markup the picture to hopefully make everything clear.
Thanks, Richard
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Wed, Oct 11, 2017 at 6:18 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Afterthought: If PADS does give impedance values, please include the values for each of the HDMI differential traces and a URL to images of the top and bottom layers of that layout.
they're all 89 ohms, single-line.
That way I'll be able to make recommendations and markup the picture to hopefully make everything clear.
appreciated... there's no differences: they're all 89 ohms. i'm assuming that's calculated from track width and board / layer widths.
capacitance is slightly different: the shorter traces (TX2) are 3.06pF, the longer ones (CK) are 3.55pF - i would imagine that the extra length results in a directly-proportionally larger capacitance?
l.
https://ez.analog.com/docs/DOC-11303
Each TMDS signal shall have single ended impedance of 50 Ω ± 10%. Each TMDS pair shall have differential impedance of 100 Ω ± 5%.
whoops.... :) 89 ohm... 50 ohm. 89 ohm... 50 ohm. oops... :)
On Oct 11, 2017, at 19:31, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
https://ez.analog.com/docs/DOC-11303
Each TMDS signal shall have single ended impedance of 50 Ω ± 10%. Each TMDS pair shall have differential impedance of 100 Ω ± 5%.
whoops.... :) 89 ohm... 50 ohm. 89 ohm... 50 ohm. oops... :)
Well, if the reported impedance is the single-ended impedance of those lines we have considerable margin to burn and should aggressively pursue the taper structure and bring in the keepouts at each end.
For the geometry that fit our constraints, we calculated a single-ended impedance of ~72 Ohm and differential impedance of ~111 Ohm (which corresponds to a tolerance of 11%).
On Thu, Oct 12, 2017 at 9:16 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
whoops.... :) 89 ohm... 50 ohm. 89 ohm... 50 ohm. oops... :)
Well, if the reported impedance is the single-ended impedance of those lines we have considerable margin to burn and should aggressively pursue the taper structure and bring in the keepouts at each end.
i sort-of understand that. am i right in thinking: at the ends we have to treat them as single-ended, and achieve a sngle-ended impedance of 50 ohms, but 100 ohms for the diff-pairs.
For the geometry that fit our constraints, we calculated a single-ended impedance of ~72 Ohm and differential impedance of ~111 Ohm (which corresponds to a tolerance of 11%).
ok so 72's not really very close to 50 ohms... interested to learn how that can be achieved.
l.
hiya richard, so how you getting on? --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Fri, Oct 13, 2017 at 1:56 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Thu, Oct 12, 2017 at 9:16 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
whoops.... :) 89 ohm... 50 ohm. 89 ohm... 50 ohm. oops... :)
Well, if the reported impedance is the single-ended impedance of those lines we have considerable margin to burn and should aggressively pursue the taper structure and bring in the keepouts at each end.
i sort-of understand that. am i right in thinking: at the ends we have to treat them as single-ended, and achieve a sngle-ended impedance of 50 ohms, but 100 ohms for the diff-pairs.
For the geometry that fit our constraints, we calculated a single-ended impedance of ~72 Ohm and differential impedance of ~111 Ohm (which corresponds to a tolerance of 11%).
ok so 72's not really very close to 50 ohms... interested to learn how that can be achieved.
l.
I'll try to get some computer time today and markup a picture with some ideas for the taper and geometry towards the connector end and send it to the list.
By the way, the Analog Devices employee's recommendations can't be exactly normative with my understanding of transmission line impedances--differential impedance < 2 * single-ended impedance. (In other words you'll want single-ended > 50Ω if you hope to get differential = 100Ω.)
I'd consider them design guidelines or goals in order to try and keep the process from going in the ditch.
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On Sun, Oct 22, 2017 at 7:33 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
I'll try to get some computer time today and markup a picture with some ideas for the taper and geometry towards the connector end and send it to the list.
thx richard.
By the way, the Analog Devices employee's recommendations can't be exactly normative with my understanding of transmission line impedances-- differential impedance < 2 * single-ended impedance. (In other words you'll want single-ended > 50Ω if you hope to get differential = 100Ω.)
that makes a kind of sense
I'd consider them design guidelines or goals in order to try and keep the process from going in the ditch.
well... in theory it might be possible to change the layer stack slightly (move layer 5 a bit further away from layer 1), or go to 4mil track widths (but preferably *without* moving any of the traces!)
the layer stack height alteration is an easy one to do.
track width changes... yyeah... 4 mil would be the thinnest tracks on the entire board, i'm reluctant to do it but we can do it if necessary.
l.
My wife was sick last week so I spent more quality time with my daughters taking them to appointments, working with them on their studies, et cetera.
I'm working on the geometry of the taper for this afternoon, but first a few questions to clarify some points.
On Sun, Oct 22, 2017 at 1:12 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Sun, Oct 22, 2017 at 7:33 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
By the way, the Analog Devices employee's recommendations can't be exactly normative with my understanding of transmission line impedances-- differential impedance < 2 * single-ended impedance. (In other words you'll want single-ended > 50Ω if you hope to get differential = 100Ω.)
that makes a kind of sense
I'd consider them design guidelines or goals in order to try and keep the process from going in the ditch.
well... in theory it might be possible to change the layer stack slightly (move layer 5 a bit further away from layer 1), or go to 4mil track widths (but preferably *without* moving any of the traces!)
the layer stack height alteration is an easy one to do.
track width changes... yyeah... 4 mil would be the thinnest tracks on the entire board, i'm reluctant to do it but we can do it if necessary.
I think we can get away without much of the special considerations we are spending on this and it will probably work just fine at HDMI v1.4 but moving up to higher clock speeds with the later versions will likely require more care. That said, 1. do you have a picture of the HDMI layout you referred to which is known to have worked?
I'm working under the assumption that we can leave the board fabrication parameters alone (stack thickness, smallest trace, smallest gap) and still make a working HDMI transmitter.
2. Does Mentor Graphics give any documentation to explain the provenance of the impedance numbers it reports from PADS layout?
I am somewhat surprised to hear that our impedance is higher than we calculated with the TI equations--especially since we have several incursions within the guidelines they suggested. I expected to be on the low side, not the high side, of what we designed for. Thus my initial reaction that the 89Ω value sounded more like the differential impedance which had sagged a bit (from ~110Ω) under the pressure of close copper. I expected to design for a little higher impedance with the knowledge that we would likely lose some to unavoidable spacing issues.
So if the impedance number from PADS is to be useful we really need to know what it is measuring. If it is single-ended, we are high and take measures to reduce it such as bringing ground fill closer to traces. If it is differential, then we are about 10% below nominal and we should make sure any change to the layout doesn't further lower the impedance. If it is neither, we will have to come to some understanding of what it is in order for it to be useful as design feedback.
3. How far do the differential pairs travel in the northeast direction after turning up from the bottom of the board? (Dimension 'A' in the diagram below.)
4. How far do the TX0 traces travel after turning northeast from the bottom of the board before they have to turn due north to avoid those ground vias? (Dimension 'B' in the diagram below.)
On Thu, Oct 26, 2017 at 5:36 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
My wife was sick last week so I spent more quality time with my daughters taking them to appointments, working with them on their studies, et cetera.
not a problem richard. as you may have (or probably more sensibly didn't) see, i'm taking the opportunity to focus on shenzhen maker faire and the two 3d printers, plus sensor boards, plus low-cost STM32F-based arduino-due board, plus RD3D (a major upgrade to RAMPS) and so on.
I'm working on the geometry of the taper for this afternoon, but first a few questions to clarify some points.
cool.
track width changes... yyeah... 4 mil would be the thinnest tracks on the entire board, i'm reluctant to do it but we can do it if necessary.
I think we can get away without much of the special considerations we are spending on this and it will probably work just fine at HDMI v1.4 but moving up to higher clock speeds with the later versions will likely require more care.
later versions are *never* going to go to HDMI 2.0 speeds... because there will never be a version of the A20 which can do HDMI 2.0 speeds. basically for an upgrade to HDMI 2.0 that means using a totally new SoC, that means completely starting from scratch with a completely and entirely new PCB layout.
That said,
- do you have a picture of the HDMI layout you referred to which is
known to have worked?
ha. very funny joke. as in, it's so bad that you'll laugh hysterically at how completely they failed to follow the HDMI design rules. in fact, i am sure that they actually knew them... just so as to be able to *deliberately fail* to obey EVERY SINGLE ONE OF THEM, because it is statistically significant that they actually failed to follow all of them, 100%.
it's spread out on 3 layers: CLK goes onto layer 6, TX0-2 on layer 3, there's not even the slightest effort to provide GND separation, HSCL and so on are routed within 5 mil of the diff-pairs, there's absolutely no respecting diff-pair via spacing whatsoever, intra and inter pair vias are separated by 5mil, absolutely no GND vias nearby of any kind, and the pairs don't even length-match, not inter or intra. at all. the ESD protection was all on layer 6, meaning that there were totally unnecessary via jumps from layer 3 to layer 6 and then to layer 1 just to get to the ESD and then back to the connector, all within about... 1.5mm of each other.
basically the tracks were treated as if they were ORDINARY tracks, jammed in tightly together because of space restriction down that edge of the board.
there's absolutely no chance it would pass EMI... but incredibly it did actually get 1080p30 out the connector without any kind of visual artefacts or failures to display. stunning, really.
i'm actually too embarrassed to send you any kind of pictures as it will only put you into shock. oh - when i say "no ground vias" i mean ABSOLUTELY NO ground vias whatsoever (either side), even though the HDMI tracks travel within 25 mil of the board edge for the entire distance.
the rule has appeared to be: take everything we've done here.... and do the total opposite.
I'm working under the assumption that we can leave the board fabrication parameters alone (stack thickness, smallest trace, smallest gap) and still make a working HDMI transmitter.
if the above is anything to go by, it should be pretty clear that you can get away with a hell of a lot more than expected. HDMI 2.0 absolutely no chance, but 1.4? seems to be... pretty tolerant. amazingly.
- Does Mentor Graphics give any documentation to explain the
provenance of the impedance numbers it reports from PADS layout?
not that i've ever looked for it, but i can make some guesses. it's a lot LOT simpler than you're expecting. there's absolutely no consideration taken of neighbouring GND on the same layer *whatsoever*, for example.
I am somewhat surprised to hear that our impedance is higher than we calculated with the TI equations--especially since we have several incursions within the guidelines they suggested.
the numbers have absolutely nothing to do whatsoever with neighbouring tracks. as in: the fact that neighbouring tracks exist - or not - or the fact that there may - or may not - exist any copper pour within any distance of any kind, to any part of any track, is COMPLETELY AND UTTERLY IGNORED.
the only factors taken into consideration appear to be board thickness, track length, and distance to any plane SPECIFICALLY marked as "GND".
i tested this out by changing the thickness of the substrate between Layer 1 (TOP) and Layer 2 (GND) and then compensating for that change by matching it in LAYER 3 (GND) and Layer 4 (POWER). the result was: the reported impedance of the HDMI tracks changed.
so we *can* actually adjust the impedance by altering the stack: i know a fab house that has an extremely good engineer who knows how to do that just from the gerbers alone, but i don't have access to him any more.
I expected to be on the low side, not the high side, of what we designed for.
you may be believing that i have access to "Hyperlinx" which is the Signal Integrity / Simulation package. that CAN - as best i know - do the kinds of impedance analysis that you're expecting / believing that is reported.
i do NOT have access to that package. the impedance value reported by PADS DOES NOT in ANY WAY take into account the nearby copper. not even when you actually run the flood-fill. it's simply too complicated to do (requires Signal-level electronics Simulation) and that's just not part of the PADS program: it's part of Hyperlynx.
Thus my initial reaction that the 89Ω value sounded more like the differential impedance which had sagged a bit (from ~110Ω) under the pressure of close copper.
nope. not at all. under no circumstances is PADS (on its own) capable of taking into account the closeness of any copper (pour or tracks). in the reported impedance value it COMPLETELY ignores ALL copper and ALL nearby tracks, taking into account ONLY those three parameters: length, width, and distance to any GND plane(s).
So if the impedance number from PADS is to be useful we really need to know what it is measuring. If it is single-ended, we are high and take measures to reduce it such as bringing ground fill closer to traces.
it's single-ended, and has absolutely nothing whatsoever to do with any copper on the same layer, whatsoever.
- How far do the differential pairs travel in the northeast
direction after turning up from the bottom of the board? (Dimension 'A' in the diagram below.)
5.6mm
- How far do the TX0 traces travel after turning northeast from the
bottom of the board before they have to turn due north to avoid those ground vias? (Dimension 'B' in the diagram below.)
1.3mm.
btw.. *sigh* one very important bit of info: the layer stack parameters i double-checked, i wasn't confident that they were for a 1.2mm board, and it's good that i checked.
https://www.quick-teck.co.uk/TechArticleDoc/4138811771353606590.pdf
the pre-preg distance is supposed to be 0.2mm not 0.254 to create a standard 1.2mm 6-layer stack. i had 0.254 which is for a 1.6mm. whoops.
so the actual impedance reported - now that i've modified the design rules for the stack to match 1.2mm total height, are 81 ohms.
sorry!
l.
Thank you for the very informative reply! I'm going to bed now. I look forward to sending my technical reply tomorrow.
On Sep 20, 2017, at 13:27, Richard Wilbur richard.wilbur@gmail.com wrote:
On Wed, Sep 20, 2017 at 1:57 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Tue, Sep 19, 2017 at 11:26 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
I'm interested in tracking down the power supply pins for the differential HDMI signals as that is where our return path for common-mode signal has to go.
there's no specific power pin for HDMI. the GND pins are grouped in with a whole stack of other GND pins, there's absolutely no way it's practical to get a special GND plane to it: the board is extremely full already.
I'm not looking to provide any special connection to the power or ground pins. I just want to make sure we don't obstruct the return current path any more than necessary on its way from bottom reference ground plane (layer 5) to top reference ground plane (layer 2) to the power supply pins of the differential drivers:
- ground plane (layer 2) via to SoC ground pin land (layer 1)
- ground plane (layer 2) via to power supply decoupling capacitor
ground land (layer 1), through decoupling capacitor to land on power supply trace (layer 1), through trace to SoC power supply pin land (layer 1).
The goal is to avoid unnecessarily impeding this return current path. I'm trying to avoid making the path >~200mil and putting any major obstruction (like a huge layer void) in the way.
While browsing the A20 datasheet, I found that the HDMI section does have a power pin but not labelled the way I was asking you about. Page 18 mentions that VCC-HDMI is a power pin on ball #T13. On the schematic it is connected to net HVP which has power decoupling capacitor C108 which looks like "104" => 0.1uF.
Looks like the path from the copper on layer 2 below the HDMI pins (balls #TUVW 22,23) on the SoC (processor) to the VCC-HDMI power pin (#T13) is ~300mil. It doesn't look overly impeded.
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On Tue, Jan 16, 2018 at 9:06 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
The goal is to avoid unnecessarily impeding this return current path. I'm trying to avoid making the path >~200mil and putting any major obstruction (like a huge layer void) in the way.
While browsing the A20 datasheet, I found that the HDMI section does have a power pin but not labelled the way I was asking you about.
ah ok
Page 18 mentions that VCC-HDMI is a power pin on ball #T13. On the schematic it is connected to net HVP which has power decoupling capacitor C108 which looks like "104" => 0.1uF.
yep. and a VIA to the other side (BOTTOM) C108 is about as close as you can possibly get
Looks like the path from the copper on layer 2 below the HDMI pins (balls #TUVW 22,23) on the SoC (processor) to the VCC-HDMI power pin (#T13) is ~300mil. It doesn't look overly impeded.
yehh it seems to work fine, on this design and on other boards.
l.
On Oct 11, 2017, at 18:08, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Wed, Oct 11, 2017 at 6:18 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Afterthought: If PADS does give impedance values, please include the values for each of the HDMI differential traces and a URL to images of the top and bottom layers of that layout.
they're all 89 ohms, single-line.
That way I'll be able to make recommendations and markup the picture to hopefully make everything clear.
appreciated... there's no differences: they're all 89 ohms. i'm assuming that's calculated from track width and board / layer widths.
capacitance is slightly different: the shorter traces (TX2) are 3.06pF, the longer ones (CK) are 3.55pF - i would imagine that the extra length results in a directly-proportionally larger capacitance?
I think you are probably correct here. I think the capacitance has to do with length of trace near other copper (same layer or not) and separation distance between the trace in question and the other copper. Also the area of the trace and other copper which are facing each other.
Which layout are these measurements coming from? Is it pictured at a publicly available URL?
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Thu, Oct 12, 2017 at 7:30 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Oct 11, 2017, at 18:08, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Wed, Oct 11, 2017 at 6:18 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Afterthought: If PADS does give impedance values, please include the values for each of the HDMI differential traces and a URL to images of the top and bottom layers of that layout.
they're all 89 ohms, single-line.
That way I'll be able to make recommendations and markup the picture to hopefully make everything clear.
appreciated... there's no differences: they're all 89 ohms. i'm assuming that's calculated from track width and board / layer widths.
capacitance is slightly different: the shorter traces (TX2) are 3.06pF, the longer ones (CK) are 3.55pF - i would imagine that the extra length results in a directly-proportionally larger capacitance?
I think you are probably correct here. I think the capacitance has to do with length of trace near other copper (same layer or not) and separation distance between the trace in question and the other copper. Also the area of the trace and other copper which are facing each other.
i honestly don't know if PADS is that sophisticated. the Lynx SI add-on (which is... tens of thousands of dollars) certainly will be.
Which layout are these measurements coming from? Is it pictured at a publicly available URL?
no change in a week. i'll always update the news page and send a message here indicating that i've done that. latest will always be here http://rhombus-tech.net/allwinner_a10/news/ - i will always add the latest image onto the end of the latest news.
so at this time, right now, that will be http://rhombus-tech.net/allwinner_a10/news/eoma68-a20-275-hdmi-new-wiggles-l...
l.
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On Wed, Oct 11, 2017 at 5:58 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Your change to TX1 definitely looks like an improvement.
In order to make a determination on the best course of action regarding the keepout at the connector end and whether to recommend some type of taper I still have a burning question:
What does PADS currently give as the impedance of the HDMI differential lines?
each line is 90 ohms.
Does it give an impedance for a particular trace?
yes. 90 ohms. or... 89.
(That would likely be the single-ended impedance.) Does it offer a differential impedance value for a pair of traces?
no. from what i gather you're expected to read up on diff-pair rules.
l.
On Oct 11, 2017, at 18:04, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Wed, Oct 11, 2017 at 5:58 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
What does PADS currently give as the impedance of the HDMI differential lines?
each line is 90 ohms.
Does it give an impedance for a particular trace?
yes. 90 ohms. or... 89.
(That would likely be the single-ended impedance.)
Those are surprisingly high for single-ended impedance on that board stack and geometry. I would have expected something less than or equal to about 60 Ohm. 89 or 90 Ohm sounds more like what I might expect for our differential impedance (less than twice the single-ended impedance).
Does it offer a differential impedance value for a pair of traces?
no. from what i gather you're expected to read up on diff-pair rules.
What version of PADS Layout are you using? Mentor responded to a question about version 9.2 saying it calculates a general impedance value taking into account:
"PADS uses Diff Pair gap value and the two nearest planes (Cam or Split/Mixed) to calculate trace impedance; if the trace goes between two planes (Stripline), or just one trace to the nearest plane (Micro Stripline) in other case. Cut outs are ignored for both cases."[*]
Reference: [*] https://communities.mentor.com/thread/5743
richard re image, yes yellow vias moved as far as possible, actually deleted the top right one as there's components (ESD) in the way on layer 1.
I have a question about one of the traces: In the layout picture it appears that something resembling a via coincides with HTX1P following the second wiggle after the trace turns NE. If it is a via, what is it doing there? If not, what is it?
I would recommend if you want to be able to solder or desolder by hand the μHDMI connector to/from the board that you use thermal relief (multiple spokes emanating from the land) when connecting ACIN-5V to pin 19. On the other hand, this solid layout does make a lower impedance connection for power and should work fine in the surface-mount oven for soldering as long as you have solder resist covering the trace outside the ESD land for pin 19.
Of course, hopefully you never have need of soldering or desoldering the μHDMI connector by hand. Looks best left to the oven.
On Wed, Aug 30, 2017 at 7:59 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
I have a question about one of the traces: In the layout picture it appears that something resembling a via coincides with HTX1P following the second wiggle after the trace turns NE. If it is a via, what is it doing there? If not, what is it?
you've lost me, sorry. i don't know if you have access to an image editor but an arrow pointing would help - i know you're using an iphone so that might be a leetle awwkward...
Of course, hopefully you never have need of soldering or desoldering the μHDMI connector by hand. Looks best left to the oven.
yyeah this connector is a bitch to take off by hand. the heatgun literally melts the plastic inside the case and that's it, it's done - in the bin. with the added risk that it can strip off the pads on its way up.
then when you try and put a replacement on, that melts too, the pins move off the same plane and it's game over for *that* connector, too.
this is why we'll be doing a test run of some low-cost 2-layer PCBs (1in x 1in) just with the DC3 land pattern and some test jumpers, which will go through the oven to make sure that the DC3 actually sits down and all pins connect to their pads.
lot less risky than $USD 2,000 for complete PCBs only to find that after 5-8 weeks yet another footprint layout doesn't work.....
l.
I'm working on replies to both of your last two messages and hope to send them in the next 6-12 hours. I'm trying to finish some other stuff while I have sunlight.
On Wed, Aug 30, 2017 at 4:07 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Wed, Aug 30, 2017 at 7:59 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
I have a question about one of the traces: In the layout picture it appears that something resembling a via coincides with HTX1P following the second wiggle after the trace turns NE. If it is a via, what is it doing there? If not, what is it?
you've lost me, sorry. i don't know if you have access to an image editor but an arrow pointing would help - i know you're using an iphone so that might be a leetle awwkward...
Borrowing my wife's laptop I used the bundled Paint program to scratch some marks on the image from your wiggles progress message. What I'm referring to has been in the layout pictures for a while longer than the image I used to note it and I was curious but had bigger fish to fry.
Of course, hopefully you never have need of soldering or desoldering the μHDMI connector by hand. Looks best left to the oven.
[...]
this is why we'll be doing a test run of some low-cost 2-layer PCBs (1in x 1in) just with the DC3 land pattern and some test jumpers, which will go through the oven to make sure that the DC3 actually sits down and all pins connect to their pads.
lot less risky than $USD 2,000 for complete PCBs only to find that after 5-8 weeks yet another footprint layout doesn't work.....
Good plan.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Fri, Sep 1, 2017 at 5:01 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Wed, Aug 30, 2017 at 4:07 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Wed, Aug 30, 2017 at 7:59 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
I have a question about one of the traces: In the layout picture it appears that something resembling a via coincides with HTX1P following the second wiggle after the trace turns NE. If it is a via, what is it doing there? If not, what is it?
you've lost me, sorry. i don't know if you have access to an image editor but an arrow pointing would help - i know you're using an iphone so that might be a leetle awwkward...
Borrowing my wife's laptop I used the bundled Paint program to scratch some marks on the image from your wiggles progress message.
*grin*
What I'm referring to has been in the layout pictures for a while longer than the image I used to note it and I was curious but had bigger fish to fry.
ah! ok, i know what it is - it's the centre mark of a big pad on the layer below. nice feature (gets in the way, here) - the centre of a pad is marked with a to-scale circle that is displayed on all layers. in this case, as that's a 1206 component the circle is huuuge.... and coincidentally the same size as a VIA :)
so... can be safely ignored.
l.
On Sep 1, 2017, at 12:01, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
ah! ok, i know what it is - it's the centre mark of a big pad on the layer below. nice feature (gets in the way, here) - the centre of a pad is marked with a to-scale circle that is displayed on all layers. in this case, as that's a 1206 component the circle is huuuge.... and coincidentally the same size as a VIA :)
so... can be safely ignored.
Thank you for setting my mind at ease.
On Aug 29, 2017, at 18:54, Richard Wilbur richard.wilbur@gmail.com wrote:
Shortening CX and TX0 is fine but I would cramp any of the clearances to make it happen.
Sorry for any misconceptions. I meant to say:
"Shortening CX and TX0 is fine but I would not cramp any of the clearances to make it happen."
On Wed, Aug 30, 2017 at 2:14 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Aug 29, 2017, at 18:54, Richard Wilbur richard.wilbur@gmail.com wrote:
Shortening CX and TX0 is fine but I would cramp any of the clearances to make it happen.
Sorry for any misconceptions. I meant to say:
"Shortening CX and TX0 is fine but I would not cramp any of the clearances to make it happen."
ah! luckily that can't be done anyway :)
On Aug 22, 2017, at 10:09, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
SATA was on a very preliminary version of EOMA68. it was cut a long time ago.
Sorry for bringing up old news.
On Tue, Aug 22, 2017 at 4:30 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Regarding SD0: To what interface does it belong? What is the maximum data rate on this line?
MicroSD card reading (and other SD/MMC / SDIO compatible interfaces). i *think* it's a max datarate of 50mhz....
Sounds like SD0 is high-frequency single-ended so it might warrant a ground shield trace--if there's room. But I would rather maintain the 15mil differential pair trace to any other trace spacing because I'm guessing the coupling to differential pairs will be small. (It is not parallel to differential signals for a significant distance, is it?)
On Wed, Aug 23, 2017 at 8:04 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Aug 22, 2017, at 10:09, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
SATA was on a very preliminary version of EOMA68. it was cut a long time ago.
Sorry for bringing up old news.
ey no problem it's all interesting stuff
MicroSD card reading (and other SD/MMC / SDIO compatible interfaces). i *think* it's a max datarate of 50mhz....
Sounds like SD0 is high-frequency single-ended so it might warrant a ground shield trace--if there's room.
there is... just!
But I would rather maintain the 15mil differential pair trace to any other trace spacing because I'm guessing the coupling to differential pairs will be small. (It is not parallel to differential signals for a significant distance, is it?)
nono - they run round the back of the vias (attached) - yellow, 6 lines.
l.
On Wed, Aug 9, 2017 at 7:23 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
next set...
wiggles.jpg is the layer 6 length-matching area: HX2N/P is the one that's the longest, it snakes back on itself. i length-matched all 3 signal pairs to 56.413, and left the CK lines at 57.134 just to give the tiniest bit of delay (TI recommendations iirc).
Very nicely done! 57.134mm - 56.413mm = 721um => T(delay) = 721um / 150um/ps = 4.8ps
That is a very tiny delay! Now that we have achieved such close synchronization, I'm suggesting we go for the next goal where we design a certain amount of inter-pair skew into the layout for purposes of lowering the strength of our synchronized pulsing data lines to a more diffuse chatter.
no - not even enough space to do 5.1mil / 5.0 clearance... just... too much.
I understand. We might end up with more room--see discussion below.
the other images show the via'd portions, they're all either symmetrical or perfectly length-matched to 0.001mm.
Again, they look nice.<div id="DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2"><br /> <table style="border-top: 1px solid #D3D4DE;"> <tr> <td style="width: 55px; padding-top: 13px;"><a href="http://www.avg.com/email-signature?utm_medium=email&utm_source=link&utm_campaign=sig-email&utm_content=webmail" target="_blank"><img src="https://ipmcdn.avast.com/images/icons/icon-envelope-tick-green-avg-v1.png" alt="" width="46" height="29" style="width: 46px; height: 29px;" /></a></td> <td style="width: 470px; padding-top: 12px; color: #41424e; font-size: 13px; font-family: Arial, Helvetica, sans-serif; line-height: 18px;">Virus-free. <a href="http://www.avg.com/email-signature?utm_medium=email&utm_source=link&utm_campaign=sig-email&utm_content=webmail" target="_blank" style="color: #4453ea;">www.avg.com</a> </td> </tr> </table><a href="#DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2" width="1" height="1"></a></div>
On Fri, Aug 11, 2017 at 12:37 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Wed, Aug 9, 2017 at 7:23 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
next set...
wiggles.jpg is the layer 6 length-matching area: HX2N/P is the one that's the longest, it snakes back on itself. i length-matched all 3 signal pairs to 56.413, and left the CK lines at 57.134 just to give the tiniest bit of delay (TI recommendations iirc).
Very nicely done! 57.134mm - 56.413mm = 721um => T(delay) = 721um / 150um/ps = 4.8ps
That is a very tiny delay!
ooooOoo :)
Now that we have achieved such close synchronization, I'm suggesting we go for the next goal where we design a certain amount of inter-pair skew into the layout for purposes of lowering the strength of our synchronized pulsing data lines to a more diffuse chatter.
*deep breath*.... aaaaaaaa! :)
well.... that actually happens for the majority of the length in the middle (starting layer 6)
but.... if i simply *take out* the intermediary wiggles on layer 6....
no - not even enough space to do 5.1mil / 5.0 clearance... just... too much.
I understand. We might end up with more room--see discussion below.
which has probably been truncated...
the other images show the via'd portions, they're all either symmetrical or perfectly length-matched to 0.001mm.
Again, they look nice.<div id="DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2">
whoops.... something melted there...
On Fri, Aug 11, 2017 at 1:36 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
ok richard, so what would you suggest for the amount of skew to be added?
Sorry about the HTML that snuck into that last message! I deleted a similar egregious amount of off-color HTML in the previous message that must be coming from one of my E-mail clients when I instructed it to reply. (I just saw it again on this message. Turns out the free anti-virus software from AVG on this M$ windows machine was configured to add an E-mail signature which looks like it was basically an HTML advertisement with URL. I disabled it so I hope to not see any more.)
My earlier message from yesterday opens the discussion of designing a certain amount of inter-pair skew into the HDMI signals. Before I give a more definitive recommendation it would be useful to know the pair lengths of each of the 3 HDMI data pairs HTX0, HTX1, HTX2, and the clock pair length HTXC before you added inter-pair skew compensation.
On Fri, Aug 11, 2017 at 4:30 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
My earlier message from yesterday opens the discussion of designing a certain amount of inter-pair skew into the HDMI signals. Before I give a more definitive recommendation it would be useful to know the pair lengths of each of the 3 HDMI data pairs HTX0, HTX1, HTX2, and the clock pair length HTXC before you added inter-pair skew compensation.
previous message. look through logs or archives. clock's 57.135. HTX2 was something like 49. others in between.
l.
On Aug 10, 2017, at 23:12, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Fri, Aug 11, 2017 at 12:37 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Wed, Aug 9, 2017 at 7:23 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
next set...
wiggles.jpg is the layer 6 length-matching area: HX2N/P is the one that's the longest, it snakes back on itself. i length-matched all 3 signal pairs to 56.413, and left the CK lines at 57.134 just to give the tiniest bit of delay (TI recommendations iirc).
Very nicely done! 57.134mm - 56.413mm = 721um => T(delay) = 721um / 150um/ps = 4.8ps
That is a very tiny delay!
I would need to do more research to make a meaningful recommendation. Sorry for bringing up a topic I wasn't prepared to discuss intelligently. Let's go with what you've done.
According to my calculations you could get away without any inter-pair skew compensation on the board whatsoever and still meet the HDMI specification for the transmitter budget. What you have done regarding inter-pair skew compensation reserves nearly all of the transmitter inter-pair skew budget from the HDMI standard for the connector and the rest of the system. This will serve to accommodate less than optimal inter-pair skew imposed by the cable and/or receiver.
Now that we have achieved such close synchronization, I'm suggesting we go for the next goal where we design a certain amount of inter-pair skew into the layout for purposes of lowering the strength of our synchronized pulsing data lines to a more diffuse chatter.
*deep breath*.... aaaaaaaa! :)
well.... that actually happens for the majority of the length in the middle (starting layer 6)
but.... if i simply *take out* the intermediary wiggles on layer 6....
Ill-founded proposal for which I don't presently have the time to improve.
no - not even enough space to do 5.1mil / 5.0 clearance... just... too much.
I understand. We might end up with more room--see discussion below.
which has probably been truncated...
Turns out we don't have the room to change the trace width or spacing without having a deleterious effect on impedance.
On Tue, Aug 15, 2017 at 12:08 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
I would need to do more research to make a meaningful recommendation. Sorry for bringing up a topic I wasn't prepared to discuss intelligently. Let's go with what you've done.
hey this is all extremely worthwhile. it's me who is barely able to follow along.
According to my calculations you could get away without any inter-pair skew compensation on the board whatsoever and still meet the HDMI specification for the transmitter budget.
ah ha!! that would be better, it's quite a mess to be honest.
What you have done regarding inter-pair skew compensation reserves nearly all of the transmitter inter-pair skew budget from the HDMI standard for the connector and the rest of the system. This will serve to accommodate less than optimal inter-pair skew imposed by the cable and/or receiver.
.... i'm translating this to mean "lose the large middle set of wiggles on TX0, TX1 and TX2". they're bugging me anyway ("beauty" criteria)
plus, we know that the very first design.. i should open that up shouldn't i... never had large wiggles and it worked fine. looking at it now, the guy who designed it had all the vias coming out from the CPU in a straight line, no diff-pair via considerations *at all*, ran the CK lines right past *all* those vias, but, butbutbut, he put CK on layer 6, TX0-2 on layer 3
i'm amazed it worked.
Turns out we don't have the room to change the trace width or spacing without having a deleterious effect on impedance.
blech :)
l.
trying the images again (adding image/png to allowed attachment types)....
On Aug 9, 2017, at 03:34, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
okaay, so this is what i've managed for the outgoing vias (layer 1), the two lengths are equal (to each other and including across all four pairs) and the relative positions of each via are identical.
Very nicely done--especially considering how tight that space is. I like the way you snuck some extra length on the traces from the closer pins and with 45 degree bends no less.
for layer 6.... faak it's tight on space down the bottom, so i simply can't get anything but "turns" in. it'll have to go dead-straight until the other end of the board, after the PMIC, where i'll then be able to correct the length differences between the CLK pair and the other pairs.
Since the digital portion of the receivers is built to specifically correlate up to 5 (out of 10) bit times of inter-pair skew (arrival time difference between differential pairs) for every pixel clock, you could think of building in some inter-pair skew as similar to spread-spectrum techniques which have been employed in communications to drop the energy peak on the carrier frequency and more recently on motherboard chipsets. The clock period for 340MHz is T(Pixel) = 1/(pixel clock) = 1/(340MHz) = 2.94ns wavelength = velocity * period = 150um/ps * 2940ps = 441mm = 17400mil So half that period = 1470ps, which at the speed of propagation is ~ 220mm ~ 8700mil. So there is our inter-pair skew budget for the whole path: differential driver, IC lead wire, pin, PCB (the part we have design control of presently), connector, HDMI cable, connector, receiver PCB, pin, IC lead wire, receiver. I believe that if we reserve one-tenth of that inter-pair skew for our transmitter PCB, we should not be unduly stressing the budget and that amounts to ~ 22mm ~ 870mils. Interestingly this is Toradex' suggested limit for skew between clock and data. The HDMI standard restricts transmitters to T(inter-pair skew) = 0.2 * T(pixel) = 2 * T(bit) = 588ps => Δl < v * Δt = 88.2mm ~= 3470mil
richard you said that the difference between all pairs should be no more than 100mil, right? but that clock should be a leetle bit longer.
I did suggest we might work towards that as a goal based on Chrontel's recommendation, but now I'm giving the spread-spectrum idea more thought and thinking we might design some inter-pair skew into the system on purpose to reduce the amplitude of EM from the constructive interference of all those (painstakingly) phase-aligned transitions. So here is one strategy to implement what I was thinking (predicated on the spread between shortest and longest data pairs being less than 0.5 * L(bit)): 1. Shortest pair becomes our reference length. 2. Other two data pairs are routed different fractions of T(bit) longer than the reference pair. 3. Clock pair is routed a larger fraction of T(bit) longer.
Hence: L(reference) = L(shortest data pair without inter-pair skew compensation) T(bit) = 294ps => L(bit) = v * T(bit) = 150um/ps * 294ps = 44.1mm ~ 1740mil Suppose we select fractions: 0.2, 0.3, 0.5(clock) then we would make L(longer data pair) = L(reference) + 0.2 * L(bit) L(longest data pair) = L(reference) + 0.3 * L(bit) L(clock pair) = L(reference) + 0.5 * L(bit) = L(reference) + 22mm
I guess I should first ask what are the differential pair lengths before inter-pair skew corrections?
CLK-pairs are 57.245 (i got them to within a thousandth of a mm! 57.245 and 57.24518 how jammy is that!!)
Now that is some great length matching! And intra-pair where it looks like it matters the most!
HX2N/P are 49.something - a hell of a big difference. luckily that one's on the outside edge so i can "wiggle" it a lot :)
The clock data difference is ~8mm ~ 310mil.
That's around an order of magnitude (factor of 10) smaller than the limit the HDMI standard imposes on transmitters and more than a factor of 2 smaller than Toradex' recommended limit.
oh... i had another go at the USB pairs, after reading all that you recommended i wasn't happy that there was skew (which i never noticed before). the USB lines worked but there would have been quite a bit of EM.
I must confess I hadn't looked at the USB traces but it sounds like a good thing. Which level of support are you providing?
arm-netbook@lists.phcomp.co.uk
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Hrvoje Lasic -
Luke Kenneth Casson Leighton -
mike.valk＠gmail.com -
Richard Wilbur