so, ahh i would say it's christmas come early but it really *is* christmas :)
i've been speaking with madhu, the head of the shakti team, they're extremely busy with a tapeout deadline of 1st january 2018, so in about a month or so's time he will have more time to talk, and it will be possible to begin properly planning.
unlike many people to whom i've pitched the idea of an entirely libre SoC, madhu instead responded, "ok sure, what would you like?". initially being rather confused by this positive response, i outlined this page http://rhombus-tech.net/riscv/shakti/m_class/ and slowly began asking more questions.
it turns out that the indian government has given him a mandate to create THE entire range of computing platforms. in speaking to him about why, well it was pretty obvious: if you were to have everyone in india buy a foreign imported smartphone - and that's just one market - it would LITERALLY bankrupt the country with the exodus of cash. so they have a law requiring that foreign countries, if they wish to sell product in india, that 70% of it must be manufactured locally. apple has apparently asked if they can work around this to get more foreign-made smartphones into india... they've been told unequivocably NO.
the sheer scale of the opportunity has not only companies - you can guess who they are - trying to bribe him to shut down the entire programme, but also companies offering free tools and more. this means that with a ZERO financial outlay it is possible to get three (only three) designs through tapeout *AND* the MVP (multi-vendor programme) which will result in around 100 sample bare dies being made (entirely free), of which maybe 30% of those can be expected to actually result in a functioning chip. that's still 30 chips for a zero financial outlay where normally the cost would be around $5m, one each at at 20nm, 28nm and one more at 40nm.
the only condition is: the entire SoC *must* be entirely libre. that's right down to the bedrock: not just the entire ASIC design but also the software stack running on it. you know the reasons why: "Intel Management Engine".
it just so happens that the overlap between what we would like to see happen and what the shakti team has been set up to achieve happen to align near-100%.
this is an incredible opportunity.
there are four main tasks / details which need to be taken care of:
* designing and specifying the SoC so that it is DESIRABLE in a specific target market or markets * finding the right team(s) of people with links to the free software community to target 3D, Video and so on. * finding a customer base large enough to warrant going to production * bridging finance (if that customer base isn't going to pay cash up-front).
now, it turns out that *IF* the processor is designed SUCH THAT it is desirable for use in the indian schools market - either as laptops, netbooks, tablets or desktop machines (laptops would be better), THEN it is a near-automatic process of getting to market, orders of 10 million units are not a problem.
note that *this is exactly what the EOMA68 Libre Laptop Housing is for*, and would be an immediate base on which to get demo units in front of people, very very quickly (just have to take care of making an EOMA68-RISCV64 Card).
so, any ideas, input etc. welcomed.
l.
On Wed, Dec 27, 2017 at 09:08:42AM +0000, Luke Kenneth Casson Leighton wrote:
so, ahh i would say it's christmas come early but it really *is* christmas :)
i've been speaking with madhu, the head of the shakti team, they're extremely busy with a tapeout deadline of 1st january 2018, so in about a month or so's time he will have more time to talk, and it will be possible to begin properly planning.
unlike many people to whom i've pitched the idea of an entirely libre SoC, madhu instead responded, "ok sure, what would you like?". initially being rather confused by this positive response, i outlined this page http://rhombus-tech.net/riscv/shakti/m_class/ and slowly began asking more questions.
it turns out that the indian government has given him a mandate to create THE entire range of computing platforms. in speaking to him about why, well it was pretty obvious: if you were to have everyone in india buy a foreign imported smartphone - and that's just one market - it would LITERALLY bankrupt the country with the exodus of cash. so they have a law requiring that foreign countries, if they wish to sell product in india, that 70% of it must be manufactured locally. apple has apparently asked if they can work around this to get more foreign-made smartphones into india... they've been told unequivocably NO.
the sheer scale of the opportunity has not only companies - you can guess who they are - trying to bribe him to shut down the entire programme, but also companies offering free tools and more. this means that with a ZERO financial outlay it is possible to get three (only three) designs through tapeout *AND* the MVP (multi-vendor programme) which will result in around 100 sample bare dies being made (entirely free), of which maybe 30% of those can be expected to actually result in a functioning chip. that's still 30 chips for a zero financial outlay where normally the cost would be around $5m, one each at at 20nm, 28nm and one more at 40nm.
the only condition is: the entire SoC *must* be entirely libre. that's right down to the bedrock: not just the entire ASIC design but also the software stack running on it. you know the reasons why: "Intel Management Engine".
it just so happens that the overlap between what we would like to see happen and what the shakti team has been set up to achieve happen to align near-100%.
this is an incredible opportunity.
there are four main tasks / details which need to be taken care of:
- designing and specifying the SoC so that it is DESIRABLE in a
specific target market or markets
- finding the right team(s) of people with links to the free software
community to target 3D, Video and so on.
- finding a customer base large enough to warrant going to production
- bridging finance (if that customer base isn't going to pay cash up-front).
now, it turns out that *IF* the processor is designed SUCH THAT it is desirable for use in the indian schools market - either as laptops, netbooks, tablets or desktop machines (laptops would be better), THEN it is a near-automatic process of getting to market, orders of 10 million units are not a problem.
note that *this is exactly what the EOMA68 Libre Laptop Housing is for*, and would be an immediate base on which to get demo units in front of people, very very quickly (just have to take care of making an EOMA68-RISCV64 Card).
so, any ideas, input etc. welcomed.
Talk to Debian for the software, obvs :) They have most things packaged somwehere and ties to Debian Edu/Skolelinux. The problem, if problem it is, is that you need a new port to do this well and that means good emulators and, eventually, fast build hardware.
RISCv64 also needs to be well supported by the Linux kernel, so you probably need to make sure that there's an easy way to build the Linux kernel (GCC build chain and GNU tools ... )
Andy C.
l.
arm-netbook mailing list arm-netbook@lists.phcomp.co.uk http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook Send large attachments to arm-netbook@files.phcomp.co.uk
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Wed, Dec 27, 2017 at 2:25 PM, Andrew M.A. Cater amacater@galactic.demon.co.uk wrote:
On Wed, Dec 27, 2017 at 09:08:42AM +0000, Luke Kenneth Casson Leighton wrote:
so, any ideas, input etc. welcomed.
Talk to Debian for the software, obvs :)
yes - on it :) debian-riscv. there's also fedora-riscv.
They have most things packaged somwehere and ties to Debian Edu/Skolelinux. The problem, if problem it is, is that you need a new port to do this well and that means good emulators and, eventually, fast build hardware.
yehyeh. right now they're running under qemu, which is not the way you're supposed to do it, but they at least have a base suite of packages compiled up, the bootstrapping's been done.
RISCv64 also needs to be well supported by the Linux kernel, so you probably need to make sure that there's an easy way to build the Linux kernel (GCC build chain and GNU tools ... )
yehyeh, the riscv-kernel has been up and running for a long time, now, the most important thing is the acceptance of the riscv-gcc patches (done recently) and also libc6 and binutils patches.
also there's an outstanding bugreport for debian which "finalises" the strings (architecture names) and the port names and also they *must* have the support of the *exact* same versions of binutils and gcc which are utilised *right* across the board for every other debian architecture.
this is absolutely critical for stability, otherwise you can't guarantee that packages will be properly compiled and dynamically link together.
so it's a chain that's slowly propagating and sorting itself out... and being handled.
what i meant by software is things like, for example... if we get a 3D engine up and running (however it's done), that *will* need mesa3d support to be made for it. and/or vulkan, and/or whatever the flavour-of-the-month for accelerated graphics happens to be.
likewise if we add a VPU, someone has to do the.... whatever-it-is, ffmpeg, gstreamer, blah-blah porting and so on.
there are lots of little details that need someone to work on *AT THE SAME TIME* as the actual hardware *ITSELF* is being developed (!!).
it's quite an interesting and tricky self-bootstrapping problem that will require quite a bit of thought and careful planning.
l.
Are the shakti processors arm based for the architecture or some new architecture or a different one.
I believe you said the M class is supposed to be less than 1W. Which sounds absolutely insane. Dunno how they will do that, but it looks interesting especially considering the blazing speed it says on the charts.
MY Bad, I sent two of these by mistake. I meant to send one to Luke exclusively... as well
On 12/28/2017 05:33 PM, zap wrote:
Are the shakti processors arm based for the architecture or some new architecture or a different one.
I believe you said the M class is supposed to be less than 1W. Which sounds absolutely insane. Dunno how they will do that, but it looks interesting especially considering the blazing speed it says on the charts.
On Fri, Dec 29, 2017 at 12:33 AM, zap calmstorm@posteo.de wrote:
Are the shakti processors arm based for the architecture or some new architecture or a different one.
They are risc-v based
On Thu, Dec 28, 2017 at 10:33 PM, zap calmstorm@posteo.de wrote:
Are the shakti processors arm based
HELL no!!! why do you think they tried to bribe him to shut the project down!! oops did i mention that on a public mailing list? mwahahaa
for the architecture or some new architecture or a different one.
RISC-V. they are however doing it as a complete reimplementation, using a design system that's based on.... Haskell :) it's like myhdl.org (which is python) except it's Haskell -> Verilog. the advantage of that is that it's REALLY quick to write stuff in... and it has the advantage of being *formally mathematically provable*. unlike Chisel, which is what the rocket-chip is based on.
also they're going for an 8 stage pipeline not 5, so the max speed is around 2.5ghz where rocket-chip gets around 1.5ghz in 40nm,
I believe you said the M class is supposed to be less than 1W. Which sounds absolutely insane. Dunno how they will do that, but it looks interesting especially considering the blazing speed it says on the charts.
120mW per core it's easily achievable. i mentioned that the EOMA68 power budget is 2.5 watts and madhu laughed: do the math, you can get 16 SMP cores into 2.5 watts :)
l.
On 12/29/2017 12:53 AM, Luke Kenneth Casson Leighton wrote:
On Thu, Dec 28, 2017 at 10:33 PM, zap calmstorm@posteo.de wrote:
Are the shakti processors arm based
HELL no!!! why do you think they tried to bribe him to shut the project down!! oops did i mention that on a public mailing list? mwahahaa
Interesting, never knew that. and yeah, probably not the best idea but meh...
for the architecture or some new architecture or a different one.
RISC-V. they are however doing it as a complete reimplementation, using a design system that's based on.... Haskell :) it's like myhdl.org (which is python) except it's Haskell -> Verilog. the advantage of that is that it's REALLY quick to write stuff in... and it has the advantage of being *formally mathematically provable*. unlike Chisel, which is what the rocket-chip is based on.
also they're going for an 8 stage pipeline not 5, so the max speed is around 2.5ghz where rocket-chip gets around 1.5ghz in 40nm,
Risc-V hmm... interesting. I know arm is based off of a Risc chip so that's why I wondered...
Any idea when these processors will be sold?
I believe you said the M class is supposed to be less than 1W. Which sounds absolutely insane. Dunno how they will do that, but it looks interesting especially considering the blazing speed it says on the charts.
120mW per core it's easily achievable. i mentioned that the EOMA68 power budget is 2.5 watts and madhu laughed: do the math, you can get 16 SMP cores into 2.5 watts :)
Wow... that's freakin awesome. Any idea when such a processor will be implemented into the eoma68 standard?
l.
arm-netbook mailing list arm-netbook@lists.phcomp.co.uk http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook Send large attachments to arm-netbook@files.phcomp.co.uk
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Fri, Dec 29, 2017 at 6:28 PM, zap calmstorm@posteo.de wrote:
Risc-V hmm... interesting. I know arm is based off of a Risc chip so that's why I wondered...
yehyeh. no RISC just means "reduced instruction set". like "drink" can describe anything from alcohol to water to coffee... MIPS is a RISC core. ARC is a RISC core. ARM is a RISC core. ARM is a RISC core. etc. etc.
power budget is 2.5 watts and madhu laughed: do the math, you can get 16 SMP cores into 2.5 watts :)
Wow... that's freakin awesome. Any idea when such a processor will be implemented into the eoma68 standard?
if standard chip design is anything to go by... probably 18 months.
l.
power budget is 2.5 watts and madhu laughed: do the math, you can get 16 SMP cores into 2.5 watts :)
Wow... that's freakin awesome. Any idea when such a processor will be implemented into the eoma68 standard?
if standard chip design is anything to go by... probably 18 months.
I wonder how long it has been being developed though so far. :)
l.
arm-netbook mailing list arm-netbook@lists.phcomp.co.uk http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook Send large attachments to arm-netbook@files.phcomp.co.uk
On Fri, Dec 29, 2017 at 6:57 PM, zap calmstorm@posteo.de wrote:
Wow... that's freakin awesome. Any idea when such a processor will be implemented into the eoma68 standard?
if standard chip design is anything to go by... probably 18 months.
I wonder how long it has been being developed though so far. :)
dunno. they're using something similar to Chisel except where chisel is written in java, bluespec (or whatever) is written in Haskell. apparently it's possible to write a processor core in about 6 weeks flat with it... and the advantages are, you can do formal mathematical proofs on it.... *because it's Haskell*. outputs Verilog or VHDL i forget which.
anyway, the integration is where it's going to get complicated. making sure the interfaces work, and pre-writing linux kernel drivers to run on FPGAs *before* committing to silicon and so on.
we _will_ have access - free - to the university's 180nm fab, which is a bit... high power and very slow these days but at least it *might* be useful to at least prove things like e.g. sd/mmc work and so on.
l.
On Wed, Dec 27, 2017 at 11:08 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
so, ahh i would say it's christmas come early but it really *is* christmas :)
unlike many people to whom i've pitched the idea of an entirely libre SoC, madhu instead responded, "ok sure, what would you like?". initially being rather confused by this positive response, i outlined this page http://rhombus-tech.net/riscv/shakti/m_class/ and slowly began asking more questions.
Love it. One of the few times national interests happen to be the same as those of the free world movement. Also amazing answer. If this goes well it will go down in history as one of those famous conversations in the early days of tech we read about.
that's still 30 chips for a
zero financial outlay where normally the cost would be around $5m, one each at at 20nm, 28nm and one more at 40nm.
So we have the chance to get a node ahead AND RISCv64 ? Awesome.
the only condition is: the entire SoC *must* be entirely libre. that's right down to the bedrock: not just the entire ASIC design but also the software stack running on it. you know the reasons why: "Intel Management Engine".
Hehehe
https://media.ccc.de/v/34c3-8762-inside_intel_management_engine
- finding the right team(s) of people with links to the free software
community to target 3D, Video and so on.
This is something that I don't get with the shakti project. How are they planning to tackle the 2d/3d/vpu problem? From my understanding there aren't any libre designs available out of the box, cpu rendering is expensive and wasteful, anything memory compression related is patented and pretty much required when talking about ddr and not gddr and their page doesn't detail anything about that. Also external gpus are out of the question for obvious reasons.
now, it turns out that *IF* the processor is designed SUCH THAT it is desirable for use in the indian schools market - either as laptops, netbooks, tablets or desktop machines (laptops would be better), THEN it is a near-automatic process of getting to market, orders of 10 million units are not a problem.
Sounds like magic to my ears.
note that *this is exactly what the EOMA68 Libre Laptop Housing is for*, and would be an immediate base on which to get demo units in front of people, very very quickly (just have to take care of making an EOMA68-RISCV64 Card).
Indeed, and it would mean you could consider getting molds done as well instead of 3d printing the cases.
so, any ideas, input etc. welcomed.
Be wary of the 20nm node. From my experience phones of that generation were the first to have overheating problems. Power leaking is very high. I know there have been some new nodes at 20nm recently with better characteristics though.
Also I'd like to see the faces of the RPi foundation if this comes into fruition. 20nm vs 40nm all libre and mainline huge volumes and at the same price ballpark as the RPi but without the cartel control they enjoy. Good luck Luke, you really deserve this.
On Thu, Dec 28, 2017 at 9:56 PM, Bill Kontos vkontogpls@gmail.com wrote:
On Wed, Dec 27, 2017 at 11:08 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
so, ahh i would say it's christmas come early but it really *is* christmas :)
unlike many people to whom i've pitched the idea of an entirely libre SoC, madhu instead responded, "ok sure, what would you like?". initially being rather confused by this positive response, i outlined this page http://rhombus-tech.net/riscv/shakti/m_class/ and slowly began asking more questions.
Love it. One of the few times national interests happen to be the same as those of the free world movement. Also amazing answer. If this goes well it will go down in history as one of those famous conversations in the early days of tech we read about.
yehyeh!
So we have the chance to get a node ahead AND RISCv64 ? Awesome.
frickin tell me about it. madhu's even been offered free access to ASIC design tools from various companies normally worth $80m. they've seen what his team did with PowerPC before they converted to RISC-V, so they know he's serious and represents the best opportunity to gain access to a MASSIVE billion+ people untapped market
- finding the right team(s) of people with links to the free software
community to target 3D, Video and so on.
This is something that I don't get with the shakti project. How are they planning to tackle the 2d/3d/vpu problem?
that's where i need help, they're primarily focussed on the CPU part. madhu is so excited and fired up by the opportunity he's been given, and also he wants to push the technology his team is designing (for very good reasons, will explain later), that he's in danger of going down the "NIH" route. he *is* however keenly aware of things like the MIAOU project.
so for my part i've tracked down the ORSOC Graphics Accelerator, a series of white papers by MIPS... *before* the dead-or-dying ImgTec took them offline - which describe how certain Vector and SIMD instructions (a 1/(x^2) instruction, and half-precision operations) and MMX instructions (bit-wise larrrge NAND/NOR zero detection) can *massively* improve plain mesa3d software operations.
also on opencores there's a series of hard macros with basic video primitives, including cabac decode and many more: dropping lots and lots of those in will go a long *long* way towards being able to tackle 2D, 3D and a VPU.
the key here though is: it is *really* necessary to find a full software team to get the userspace stuff done *at the same time* and on emulated FPGAs so that performance can be verified / estimated.
From my understanding there aren't any libre designs available out of the box, cpu rendering is expensive and wasteful,
ordinarily, yes. however.... each shakti core only takes 0.12W. we can put 16 down and still meet a 2.5 watt budget. how d'ya like _them_ apples? :)
anything memory compression related is patented
wait.... are you telling me that RISC-V's memory / instruction compression is *patented*?? if so, by whom?
and pretty much required when talking about ddr and not gddr and their page doesn't detail anything about that.
yeah forget GDDR for now. there already exists a DDR3 controller design. the DDR *PHY* however madhu wants his team to tackle that,
Also external gpus are out of the question for obvious reasons.
not for the higher-end desktop / server class units but this is a SoC... so yeah.
now, it turns out that *IF* the processor is designed SUCH THAT it is desirable for use in the indian schools market - either as laptops, netbooks, tablets or desktop machines (laptops would be better), THEN it is a near-automatic process of getting to market, orders of 10 million units are not a problem.
Sounds like magic to my ears.
f****n'A that's an understatement :)
note that *this is exactly what the EOMA68 Libre Laptop Housing is for*, and would be an immediate base on which to get demo units in front of people, very very quickly (just have to take care of making an EOMA68-RISCV64 Card).
Indeed, and it would mean you could consider getting molds done as well instead of 3d printing the cases.
... easily justifiable
so, any ideas, input etc. welcomed.
Be wary of the 20nm node. From my experience phones of that generation were the first to have overheating problems. Power leaking is very high. I know there have been some new nodes at 20nm recently with better characteristics though.
rrriiight, ok that would explain
Also I'd like to see the faces of the RPi foundation if this comes into fruition. 20nm vs 40nm all libre and mainline huge volumes and at the same price ballpark as the RPi but without the cartel control they enjoy. Good luck Luke, you really deserve this.
thx... well... we all do. i'm just the messenger, i *really* need to find the right people.
l.
2017-12-29 6:48 GMT+01:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Thu, Dec 28, 2017 at 9:56 PM, Bill Kontos vkontogpls@gmail.com wrote:
If this goes well it will go down in history as one of those famous conversations in the early days of tech we read about.
yehyeh!
I think so too. And India is very keen on becoming the next China/Taiwan/Etc. Which I think is a good thing.
This is something that I don't get with the shakti project. How are they planning to tackle the 2d/3d/vpu problem?
also on opencores there's a series of hard macros with basic video primitives, including cabac decode and many more: dropping lots and lots of those in will go a long *long* way towards being able to tackle 2D, 3D and a VPU.
the key here though is: it is *really* necessary to find a full software team to get the userspace stuff done *at the same time* and on emulated FPGAs so that performance can be verified / estimated.
2D: Skip. AMD and Vivante already do so, NVIDIA will too IIRC. The 2D accelerators were mostly for windowing systems now replaced by composting systems, including MS Windows, and other means, Androids SurfaceFlinger, etc. The missing functions are now done on 3D or CPU.
VPU: That would require also licenses from the format owners. That's going to be difficult. And the new, open, video formats are not ready. Daala, Thor, NETVC, AV1.
Something generic to offload parts of the decoding/encoding would be the best bet I guess. Avoids licenses, single format isolation. IIRC most codecs share techniques. I might be talking jibberisch, or it might be to impractical.
3D. Wasn't there a PoC from some students in the open macro's? Perhaps those guys can be hired to refine their work?
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Fri, Dec 29, 2017 at 2:25 PM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-12-29 6:48 GMT+01:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Thu, Dec 28, 2017 at 9:56 PM, Bill Kontos vkontogpls@gmail.com wrote:
If this goes well it will go down in history as one of those famous conversations in the early days of tech we read about.
yehyeh!
I think so too. And India is very keen on becoming the next China/Taiwan/Etc. Which I think is a good thing.
hell yes. i was very surprised to find, here, that the prices in Shenzhen for commodity equipment are hardly any different from USA prices [EU different as the support of the socialist system aka "welfare state" is extremely burdensome and has to be paid for by vastly higher prices].
and the cost of living is... becoming higher than london. the hostel i stayed at was unusual, $5 / day to live in a 10-bed room and it was *full of chinese people*.
2D: Skip. AMD and Vivante already do so, NVIDIA will too IIRC. The 2D accelerators were mostly for windowing systems now replaced by composting systems, including MS Windows, and other means, Androids SurfaceFlinger, etc. The missing functions are now done on 3D or CPU.
yyeah which i'm not keen on (critically relying on 3D) - that means you *have* to have OpenGL. plus if using ORSOC Graphics Accelerator it would actually be necessary to rip those features *out* of it.
ORSOC GPU is smart, it has scalable vector font support, z-buffer support, 3D polygon display and much more. really cool.
VPU: That would require also licenses from the format owners. That's going to be difficult. And the new, open, video formats are not ready. Daala, Thor, NETVC, AV1.
this is actually a really good case for using the primitives e.g. here *not* hard-coded engines: https://opencores.org/project,video_systems
Something generic to offload parts of the decoding/encoding would be the best bet I guess. Avoids licenses, single format isolation. IIRC most codecs share techniques. I might be talking jibberisch, or it might be to impractical.
no if you can do e.g. CABAC decode, or DCT, or Huffman encode.decode, you have the building blocks and things get really quick.... *without* running into patents.
3D. Wasn't there a PoC from some students in the open macro's? Perhaps those guys can be hired to refine their work?
can you point me towards it with some clues?
l.
2017-12-29 15:37 GMT+01:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Fri, Dec 29, 2017 at 2:25 PM, mike.valk@gmail.com mike.valk@gmail.com wrote:
3D. Wasn't there a PoC from some students in the open macro's? Perhaps those guys can be hired to refine their work?
can you point me towards it with some clues?
I can't seem to find it at the moment.
Did find this:
https://github.com/VerticalResearchGroup/miaow/wiki https://github.com/jbush001/NyuziProcessor/wiki https://github.com/jbush001/NyuziProcessor/wiki/Similar-Projects
Might as well be the Nyuzi one
2017-12-29 16:21 GMT+01:00 mike.valk@gmail.com mike.valk@gmail.com:
2017-12-29 15:37 GMT+01:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Fri, Dec 29, 2017 at 2:25 PM, mike.valk@gmail.com mike.valk@gmail.com wrote:
3D. Wasn't there a PoC from some students in the open macro's? Perhaps those guys can be hired to refine their work?
can you point me towards it with some clues?
I can't seem to find it at the moment.
AH it was the ORGFX now ORSOC I guess https://opencores.org/project,orsoc_graphics_accelerator
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Fri, Dec 29, 2017 at 3:24 PM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-12-29 16:21 GMT+01:00 mike.valk@gmail.com mike.valk@gmail.com:
2017-12-29 15:37 GMT+01:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Fri, Dec 29, 2017 at 2:25 PM, mike.valk@gmail.com mike.valk@gmail.com wrote:
3D. Wasn't there a PoC from some students in the open macro's? Perhaps those guys can be hired to refine their work?
can you point me towards it with some clues?
I can't seem to find it at the moment.
AH it was the ORGFX now ORSOC I guess https://opencores.org/project,orsoc_graphics_accelerator
yeah that's the one i found, too. that's the one - one of the ones - i want to fund.
l.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Fri, Dec 29, 2017 at 3:21 PM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-12-29 15:37 GMT+01:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Fri, Dec 29, 2017 at 2:25 PM, mike.valk@gmail.com mike.valk@gmail.com wrote:
3D. Wasn't there a PoC from some students in the open macro's? Perhaps those guys can be hired to refine their work?
can you point me towards it with some clues?
I can't seem to find it at the moment.
Did find this:
https://github.com/VerticalResearchGroup/miaow/wiki https://github.com/jbush001/NyuziProcessor/wiki https://github.com/jbush001/NyuziProcessor/wiki/Similar-Projects
Might as well be the Nyuzi one
ah yehhh! thank you for reminding me! yeah i forgot about his work, thank you. i know why i forgot it: i spoke to its developer, he said there's some severe limitations... something about how it was put together, it was never really intended to go above.... 50mhz (in an FPGA) or... something. there was a fundamental design flaw in other words.
might have changed since then.
but i went, "hmm, MIAOU shader engine plus ORSOC_GPU plus RISC-V core would do *really* well"
l.
On Dec 29, 2017 8:39 AM, "Luke Kenneth Casson Leighton" lkcl@lkcl.net wrote:
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Fri, Dec 29, 2017 at 2:25 PM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-12-29 6:48 GMT+01:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Thu, Dec 28, 2017 at 9:56 PM, Bill Kontos vkontogpls@gmail.com
wrote:
2D: Skip. AMD and Vivante already do so, NVIDIA will too IIRC. The 2D accelerators were mostly for windowing systems now replaced by composting systems, including MS Windows, and other means, Androids SurfaceFlinger, etc. The missing functions are now done on 3D or CPU.
yyeah which i'm not keen on (critically relying on 3D) - that means you *have* to have OpenGL. plus if using ORSOC Graphics Accelerator it would actually be necessary to rip those features *out* of it.
ORSOC GPU is smart, it has scalable vector font support, z-buffer support, 3D polygon display and much more. really cool.
Don't know if opengl is a hard dependency now that vulkan is out there.
arm-netbook@lists.phcomp.co.uk
-
Andrew M.A. Cater -
Bill Kontos -
Louis Pearson -
Luke Kenneth Casson Leighton -
mike.valk＠gmail.com -
zap