On Mon, Dec 18, 2017 at 5:16 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Sun, Dec 17, 2017 at 9:05 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
so... ah.... key question here... is the taper needed or not? :)
The taper is a nice idea for changing the context smoothly but it requires enough space that we can't return to our original context before the cable connector (which is specified to be 100 Ohms). So I think we're better off living with the small, brief discontinuities due to incursions into our design geometrical constraints, than introducing a hulking change in our design geometrical constraints to cover up the incursions (with the likely effect of changing our impedance) and having no space left to taper the new impedance to 100 Ohm at the connector.
aw poop! i went to all the trouble of writing a parser for PADS :)
should i instead be just setting 15mil clearance all round? (and put a GND keepout underneath the ESD)?
Are there signals beneath the ESD components on layer 3 or 4?
it seems i am sensible enough not to have done that :)
If not, we could put our ground reference planes on those layers under the ESD components which would move them both one layer deeper. (We already have several conveniently placed ground vias.) Otherwise, I would just copy the lands for the ESD pads connected to the high-speed signals and put them as ground keepouts on the normal ground reference planes.
makes sense to me
(In other words, only keep out the copper on the reference plane just under the signal path where it goes through a wide pad for the ESD component.)
including the 5 mil track *between* the ESD pads, or excluding that? so literally just the ESD pads, yeah?
Likewise with the connector, I would put a ground keep out under the lands on layer 2 (probably best to just draw a keepout under the whole connector on layer 2)
including for the HSCL, HHPD and even the GND pads? of course there's VIAs connecting the tracks in between the diff-pairs
but allow layer 5 to provide a full ground shield. (Provided my assumption is correct that the connector is soldered on layer 1.)
it is.
l.
