On Tue, Sep 22, 2020 at 5:13 PM Richard Wilbur richard.wilbur@gmail.com wrote:
On Sep 18, 2020, at 07:09, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote: […]
i got up and running on an FPGA a couple weeks ago (Versa ECP5) https://www.youtube.com/watch?v=72QmWro9BSE
Congratulations on the success of booting the libre SoC on FPGA. Which processor instruction set architecture are you folks using?
OpenPOWER ISA.
Looks like the toolchain for that FPGA has a free/libré license?[*]
yes. nextpnr5, developed by daveshah and others. yosys talks to that, through something called trellis.
Did I misread the Lattice Semiconductor announcement?
no - the *lattice* toolchain is proprietary.
If it’s really free/libré I might have to save my pennies for one of those boards!
nextpnr5 is a bitch to compile because it uses python-boost by default. all you need do there is compile "--disable-boost --disable-python" or something like that, you'll have to investigate, and you get a non-GUI toolchain (you don't need or want the GUI anyway).
i recommend getting both the ulx3s https://www.crowdsupply.com/radiona/ulx3s
*and* also the VERSA-ECP5 https://nl.mouser.com/ProductDetail/Lattice/LFE5UM-45F-VERSA-EVN
the reason is because the VERSA-ECP5 has a 1 gigabit DDR3 IC on it, plus some other stuff that the ULX3S doesn't have, *but* the ULX3S has an SDRAM IC which is a lot simpler, is SDR, and so we can sort-of test against that and then have reasonable confidence that the ASIC will work. ULX3S also has an SDcard slot on it.
l.