On Tue, Jul 4, 2017 at 4:15 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Jul 4, 2017, at 02:27, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
ok richard i've redone the layout, and published 3 images here: http://rhombus-tech.net/allwinner_a10/news/
Thanks for letting me know. I took an initial peek at the images and they look like you addressed the points I mentioned.
yay
I'm going to be a day or two getting back with more detailed questions as today is a holiday here and we have family visiting till Thursday.
nice
A couple questions that spring immediately to mind:
- How continuous are the ground planes under the differential pairs? (Are there voids in the ground planes under the differential pairs?)
no. layers 2 and 5 are solid ground planes. vias obviously go through those , full vias only. non-GND vias also obviously create small interruptions but that's all
- The intra-pair length sounds well-matched, my understanding of the inter-pair skew is that the requirement is in terms of the clock speed Δt <= 0.2 Tcharacter. For 225 MHz clock the application note spoke of 888ps. So we'll be interested in determining the maximum clock rate and speed of propagation.
3e8 m/sec * 888e-12 = 0.2664 metres.... which is 266.4 mm... way beyond anything which would indicate some kind of problem if the board is 78mm long and the skew is only 2mm.
I'll also have some questions about dimensions and geometry.
ack.
Thank you for the opportunity to participate.
always appreciate the help.
l.