1 Jan
2020
1 Jan
'20
8:37 p.m.
On Tue, 31 Dec 2019 23:02:51 +0000 Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On 12/31/19, David Niklas doark@mail.com wrote:
Maybe I have not been clear, how does signing an agreement or joining UC "vet" people? I always thought that my code/schematics vetted me as a fool or a wise man.
it's not that simple when it comes to collaboration where it really matters if incompatibilty is hosed.
<snip>
That's a really interesting reply. Do you mean that there is no way to pretest changes, say with an FPGA and only Silicon will prove the design? Or is there no ongoing testing? Or what?
Thanks, David