On Sat, May 2, 2015 at 8:32 PM, Paul Boddie paul@boddie.org.uk wrote:
Moreover, the RISC-V architecture on which lowRISC is based has David Patterson on board, who was the originator of Berkeley RISC which was developed further into SPARC, so we're not talking about a group of pundits waiting for other people to do the work. Indeed, there's a RISC-V core that has supposedly been "proven" on/for various manufacturing processes, so those people aren't messing around.
(1) the goal is clearly stated as "to produce a working core that may be used by anybody".
(2) in order to restrict the amount of work that is to be done, they are *not* going to add any kind of "accelerated" instructions. no SIMD, no special decoder instructions, no video acceleration instructions, no 3D acceleration instructions - nothing.
in other words they're going to spend $USD 5m to produce a chip that contains *NO* VPU, *NO* GPU, no hardware acceleration of any kind.
now, when they say "yeah sure anybody may use the resultant core we design", that's completely and utterly useless because it's the *spending $USD 5m* that's the primary barrier!!
with $USD 10m, i can - right now - go and contact ICubeCorp, and re-activate the plans that were set up 2 years ago to produce a mass-volume SoC that would be *far more commercially viable* than what the RISC-V team are attempting to do. at least ICubeCorp's processor design has been made by someone who worked for ATI, NVIDIA _and_ AMD in their 3D / VPU division.
you want a SoC that doesn't have any kind of accelerated video or graphics? go get one of the TI beaglebone ARM Cortex A8s for goodness sake. or go get the latest dual-core ARM Cortex A5 form ATMEL, even the Zync 7030 would be better as at least you could use the FPGA to do... *something*.
honestly, then, unless someone has beat some sense into them, the RISC-V project is pretty much guaranteed to be yet another "Open Flop", where money is poured into yet another expensive lesson.
kinda annoying, but there you go.
l.