arm-netbook

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1076 discussions

RK3399
by Luke Kenneth Casson Leighton 17 Jan '18

17 Jan '18

thank you very much to the anonymous person who pointed me at a *FULL* Rockchip RK3399 Reference Design including Technical Reference Manuals, full schematic file and full PCB CAD design files. using that design it will be possible to create an amazing CPU Card... unfortunately running MALI. http://rockchip.wikidot.com/rk3399 this shows that it has USB3 however it does not have RGB/TTL, so it will be necessary to do a conversion from MIPI to RGB/TTL with an SSD2828 or similar. the Reference Design has twin 32-bit-wide LPDDR3 ICs so there is the possibility of getting not just decent performance but also low power at the same time. l.

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Early UART output vs. housing board discovery
by Jonathan Neuschäfer 17 Jan '18

17 Jan '18

Hi, what follows are a few questions/remarks/misunderstandings regarding the UART pins during early boot. In the EOMA68 specification, the section "Start-up procedure"[1] specifies that "It is required that all pins be disabled (floating tri-state) with the exception of the I2C Bus, the 5.0v Power and the Ground Pins.", which would mean that *any software* running on a CPU card is required to check the housing board's EEPROM before it may output any data on the UART, if I read it correctly. This would make early debugging harder, because EEPROM detection has to be integrated in very early code, and early code can't simply use the UART as an unconditional debug channel, that's guaranteed to reach the outside of the card, anymore. The section "Requirements for UART"[2], however, states: "As this problem is to be taken care of on the I/O Board[3] it is worth observing that CPU Cards do not require UART buffering.", suggesting that the "Start-up procedure" section simply left out UART as one of the interfaces that do not need to be tri-stated by mistake. But I am unclear about the part "CPU Cards do not require UART buffering": - Does it mean that CPU cards do not require the housing board to perform UART buffering, because they do it themselves? - Or does it mean that CPU cards are not required to perform UART buffering? So, can a CPU card assume that it may use the UART right after reset, without first consulting the EEPROM? (I understand that if a housing board has, for example, a Bluetooth module connected to the UART, something must make sure that none of that early debug output reaches the BT module, but I guess one could easily enough have a GPIO pin that controls whether the UART is cut off from the BT module, and the OS could toggle this pin once it knows that it won't send debug output anymore. The same GPIO pin might also control if the Bluetooth module is powered up at all.) Best regards, Jonathan Neuschäfer [1]: https://elinux.org/Embedded_Open_Modular_Architecture/EOMA68/Hardware#Start… [2]: https://elinux.org/Embedded_Open_Modular_Architecture/EOMA68/Hardware#Requi… [3]: As a side-note, the term "I/O Board" is a little bit unclear to me: Both CPU cards/boards and housing boards perform I/O. I figured that "I/O board" means "housing board", but I (personally) think the spec would be clearer if it talked about "housings" or "housing boards" in the first place.

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HDMI High-Frequency Layout: Recommendations
by Richard Wilbur 17 Jan '18

17 Jan '18

HDMI Layout Notes for EOMA68 Cards by Richard Wilbur Thu 3 Aug 2017 Recommendations for this Layout Source (processor) end: Could we shrink the via pitch between constituents of a differential pair (bring the vias of a differential pair closer to each other) and combine the anti-pads into an oval shape on each layer? This reduces fringing fields and thus parasitic capacitance. I like the ground vias close to the signal vias between differential pairs. It would be lovely to get a ground via close to the via on HTX2P and possibly move the one between HTX2N and HTX1P closer to the signal vias (if the signal vias of pairs can be moved closer with combining the anti-pads). What is the intra-pair skew from the processor lands to the first signal vias? I wonder if we could move the vias on the short lines a little further from the processor and make up some of the skew in that segment before we leave it? Sink (connector) end: Same thing for differential pair vias--HTX0 and HTX2--it would be lovely to shrink the via pitch and combine anti-pads (if possible). Again, I like the ground vias close to the signal vias HTX2P, HTX2N, and HTX0P. It would be lovely to be able to either put a new ground via closer to the signal via on HTX0N or move the one on the ground shield trace closer. I like what you were showing on the video with the signal vias at the connector lands: putting a neck on the trace between the via and the land should dampen the spirits of the solder but not the signals. If we could reduce the signal via pitch by combining anti-pads at the connector, we might be able to move the HTX1P and HTXCN signal vias to the other side of the lands next to the other side of the differential pair, thus equalizing the skew on the segment between the ESD chip pads and the connector pads. If that worked the final touch might be to add a ground via between DC3 pin 10 (GND) and the board edge for return current paths. Other than that, I would try and move as much of the skew compensation close to the source of the skew as possible. I'm not sure what I'm looking at as you mentioned the ground reference planes were solid under the HDMI differential pairs, but it looks like they have voids under the signals in the pictures. Am I seeing a negative, that there are only little strips of conductor in the ground reference plane directly under the high-frequency lines? Neither of these interpretations is very satisfactory, nor do they seem to represent reality. Please let me know what can and can't be done and I will adjust recommendations accordingly.

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http://www.nano-di.com/dragonfly-2020-pro
by Luke Kenneth Casson Leighton 10 Jan '18

10 Jan '18

oooo i want one! this can do 4 mil track widths and 5 mil clearance... it could handle the EOMA68-A20 PCB no problem whatsoever! that's 5mil tracks, 5mil clearance. for the RK3288 however it would not do the job: that has 0.6mm pin-pitch BGA and eMMC and you need 3mil track widths and 3mil clearance for that.... this is getting really exciting, this 3D printing of PCBs. l.

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Re: [Arm-netbook] Crowsupply update
by Pičugins Arsenijs 09 Jan '18

09 Jan '18

> software-wise i need something that does nothing more complex than > mount stuff on a micro-sd card, show boot messages on both screens, > and maybe has 2 keyboards plugged in (one into each USB socket) so > that they can bash some keys and see that crud comes up on-screen for > each. > > going beyond that... testing I2C, UART and the GPIO.... *sigh*... > that involves writing some software. Speaking about I2C, UART and GPIO testing - it sounds easy. I don't yet know which defects you'd want to cover with tests (mechanical, soldering, faulty parts, maybe all of them), but, as far as my research goes, you can test both UART and GPIOs with a loopback test, and I2C could be tested using a simple device - such as an EEPROM. Now, I don't have as much testing experience, but I've done a couple of DIY jigs - not automated, but that's yet to come - and I've been thinking about a way to make testing jigs. First thing is - it's best if the test program runs on the computer card itself. I see that's what you plan to do, and, if I'm not mistaken, cards are going to boot from a MicroSD card anyway - which is what's needed. Testing GPIOs can be done easily from software - connect GPIOs in pairs using resistors (say, 470ohm, just in case one of GPIOs is shorted to ground/VCC for some mechanical reason). Set first GPIO as input, second as output, then toggle the second GPIO and check that value that's read from the input is the same as value that's on the output. With more complicated interfaces, it depends. I2C should be testable by using an I2C device - since you have an EEPROM inside the card, it makes sense to first test if that's accessible, then test another device that's located in the test header (say, a GPIO expander or an ADC, you could use both of those for testing, too.) You can test SPI in loopback mode by connecting MISO and MOSI together, though you won't test SCK and CS that way. UART should easily be testable with a loopback - though I think you won't want to have the loopback hard-wired, to make sure that U-Boot messages won't get into U-Boot input and stop the boot process, or something of that kind =) If you want to test USB, you don't even need to have engineers mash on the keyboard, attach two USB devices with unique IDs (say, CP2012 - you can program those through USB connection) and make sure they're recognized - in case of CP2012, you can make a loopback test of their UART, just to make sure data passes through... Not sure how much sense it'll make, though =) Now, speaking about SDIO and parallel video interfaces that you have in EOMA68 pinouts, I have no idea how to test them automatically =( But the test I listed cover most mechanical pins, and half of the peripherals, which is already pretty good for avoiding RMAs of cards with bad solder joints in the USB or I2C lines. They're also cheap enough in terms of hardware& software required. So, the end result could be: a MicroSD card with a stripped down image of something something Linux that boots as quickly as possible (with cruft like networking disabled), shows the boot log on HDMI monitor - then draws a table on the monitor (I imagine it being a fullscreen application working with framebuffer, to avoid having to wait for X to load). Cells of that table would be filled with green or red, depending on whether tests pass on fail - and an all-green monitor would indicate all is well =) This should make for streamlined&quick testing and avoid lots of manual work (excluding that, well, you still have to plug the card into the testing jig and plug the cables in). Now, I don't have *that* much experience, I don't know which failures you want to protect against, but if I were to test these cards, this is what I'd do. Cheers! Arsenijs

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Software as a Community Service
by Jean Flamelle 08 Jan '18

08 Jan '18

In an ideal global community, there would be distributed to every language-bearing living being a modicum of electronic networking and information rendering hardware. That isn't going to be any day soon. I identify with arguments against SaaS,---and posed them to Urbit's bugtracker in issue 911---however software as a community service, without any potential for personal or collective gain that couldn't achieved by any kek of equal mind without prior reputation or special location, will include people who cannot effectively have compiled or rendered on their own. I would like to hear the arguments against ubuntu's launchpad buildbots specifically, because, if there are none specific to that case, I contend that every major libre project should host a ppa on launchpad to include the people of Africa and the Orient with limited devices not to mention youths of the world with limited support from their living communities stuck in highly restrictive computing environments lacking digital sovereignty over a physical device.

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Re: [Arm-netbook] EOMA68 / Libre RISC-V team financing
by ronwirring＠Safe-mail.net 07 Jan '18

07 Jan '18

-------- Original Message -------- From: Luke Kenneth Casson Leighton <lkcl(a)lkcl.net> Apparently from: arm-netbook-bounces(a)lists.phcomp.co.uk To: Linux on small ARM machines <arm-netbook(a)lists.phcomp.co.uk> Subject: [Arm-netbook] EOMA68 / Libre RISC-V team financing Date: Wed, 27 Dec 2017 09:59:04 +0000 > i find sources of funds Have you considered talking to http://www.lowrisc.org/? I do not think they have money. Maybe lowrisc can direct you to paid tasks. > arm-netbook mailing list arm-netbook(a)lists.phcomp.co.uk > http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook > Send large attachments to arm-netbook(a)files.phcomp.co.uk

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will orange pi zero run libre version of freedombox?
by ronwirring＠Safe-mail.net 06 Jan '18

06 Jan '18

http://www.orangepi.org/orangepizero/ One or more of the freedombox images are libre software? Is there a libre software version of freedombox, which will run on the orange pi 0? Thank you.

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Re: [Arm-netbook] HDMI High-Frequency Layout: Recommendations--Taper
by Richard Wilbur 06 Jan '18

06 Jan '18

The goal of the taper is to minimize the reflection coefficient involved with changes in impedance caused by changes in transmission line geometry. In essence we are trying to make the changes so gentle that we don't scare any electrons. The scared electrons reflect at the point of abrupt changes in impedance(flee back in the direction they came from) which weakens the signal delivered to the HDMI cable and, finally, the display. (Forgive the anthropomorphization of the electrons--it is purely for illustrative purposes.) As the high-frequency differential lines traverse the board from processor pin to connector pin certain parts of the geometry and electromagnetic environment stay fairly constant, other aspects in certain places are not conducive to the transmission environment needed by the HDMI signals we wish to deliver to the connector. Three principles are at work here: 1. Whatever conditions are apparent over the majority of the conduction path will dominate the transmission characteristics. (You could think of the overall impedance as being similar to a length-weighted average of the local impedance of all the sections along the path.) 2. The abruptness of changes in geometry will determine the abruptness of changes in impedance and thus the reflection coefficient associated with the perturbation. 3. Reflections are more troublesome the further you get from the signal source. Close to the source the reflection arrives at the source during the signal rise time and can be overcome by the line driver. The trace width stays mostly constant at 5mil except for component pads at processor, ESD chip, and connector and the two through-hole vias used to transition from layer 1 (processor) to layer 6 (room for differential microstrip transmission lines) back to layer 1 (connector). Both the signal trace copper thickness and the dielectric thickness between signal traces and ground plane change only at the signal vias. The room available on layer 6 allows us to make a controlled-impedance differential transmission line for a good share of the transmission path. Since the HDMI standard specifies 100 +/-15% Ohm impedance, we have designed the geometry to provide a characteristic impedance close to the upper end of the tolerance of the nominal impedance. We have room to impose this geometry for most of the length of the sojourn. At both ends the space is restricted such that the close quarters will no doubt result in a lower local impedance. Where we have room, the distance between a differential pair and any other copper (be it another differential pair or ground) is 15mil. At both ends this is restricted by the spacing between lands in the component layouts down to 5-7mil. From the first principle, we see that the influence of the lower local impedance from the restricted sections will serve to lower the overall impedance. In order to stay within the tolerances of the nominal impedance we attempt to limit the length of the restricted sections (where the inter-pair distance <15mil). In some places this could lead us to maintain 15mil inter-pair distance right up to an obstruction which imposes a 5-7mil inter-pair distance. The second principle leads us to recognize this is an abrupt change and expect that it will cause reflections. The third principle suggests it is more important to deal with abrupt changes at the connector end of the transmission line than the processor end. Hence, we are exploring the feasibility of tapering the inter-pair distance down from 15mil to 5mil as we get to the connector end, in order to soften the effects of the unavoidable space restrictions at the connector end. The other important point is that since we are dealing with differential signals, we are interested in trying to maintain symmetry in dealing with the two traces of each differential pair, lest we push signal energy into common-mode. The idea was inspired by my reading of a discussion on "Microwaves101"[*] of an impedance taper first described by R. W. Klopfenstein in a paper titled "A Transmission Line Taper of Improved Design", published in the Proceedings of the IRE, page 31-35, January 1956. We aren't really doing his work justice as our frequencies are so low that our board is too small to accommodate the length required to get the good low frequency response he demonstrates. Nevertheless, we are interested in making the sequence of small transitions in a somewhat similar fashion. Transmission Line geometry (widths) North ground fill keep out Inter-pair Distance = 15mil HDMI TX2P trace = 5mil Intra-pair Spacing = 5mil HDMI TX2N trace = 5mil Inter-pair Distance = 15mil HDMI TX1P trace = 5mil Intra-pair Spacing = 5mil HDMI TX1N trace = 5mil Inter-pair Distance = 15mil HDMI TX0P trace = 5mil Intra-pair Spacing = 5mil HDMI TX0N trace = 5mil Inter-pair Distance = 15mil HDMI TXCP trace = 5mil Intra-pair Spacing = 5mil HDMI TXCN trace = 5mil Inter-pair Distance = 15mil South ground fill keep out Adding this up yields a total = 135mil When we scale the Inter-pair Distance = 5mil, the total = 85mil This drops 50mil in width. <step> <Inter-pair Distance> <Change> 0 15mil 1 14mil -1mil 2 13mil -1mil 3 12mil -1mil 4 10mil -2mil 5 08mil -2mil 6 07mil -1mil 7 06mil -1mil 8 05mil -1mil If we use 15mil along the signal conduction path from the onset of one change to the next and 45 degree turns to initiate and complete all the changes, and if we choose a geometry to lengthen TXC (clock) the most and leave unchanged TX2, the length along the signal path of the taper will be 7*15mil + 4*1mil = 109mil after which we have no need of manual keep outs for the ground fill as the board rule of 5mil minimum Cu-Cu spacing will suffice. Deviations from path in due NorthEast direction (+ signifies change in the NorthWest direction, - signifies change in the SouthEast direction, units in mil) <step> <Northern keepout> <TX1> <TX0> <TXC> <Southern keepout> 0 0 0 0 0 0 1 -1 1 2 3 4 2 -1 1 2 3 4 3 -1 1 2 3 4 4 -2 2 4 6 8 5 -2 2 4 6 8 6 -1 1 2 3 4 7 -1 1 2 3 4 8 -1 1 2 3 4 Diagram attached below. Good grief that took awhile! I'm now completely sold on the concept of Computer-Aided Design (I've used some awkward implementations before but this was done with pencil, pen, measuring tape, and book spine for straight edge). Reference: [*] https://www.microwaves101.com/encyclopedias/klopfenstein-taper

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Meltdown and Spectre
by Louis Pearson 05 Jan '18

05 Jan '18

Has anybody else seen the recently published exploits Meltdown and Spectre? Here's a link: https://meltdownattack.com/ I'm wondering if this will increase in Risc-V processors, as most will not be vulnerable to this exploit. It relies on speculative and out-of-order execution which most current Risc-V processors do not have.

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